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66 commits

Author SHA1 Message Date
Scott Wood
25efd99dbb nand_spl: store ecc data on the stack
Adapt the following patch from spl to nand_spl:

  Author: Stefano Babic <sbabic@denx.de>
  Date:   Thu Dec 15 10:55:37 2011 +0100

      nand_spl_simple: store ecc data on the stack

      Currently nand_spl_simple puts it's temp data at 0x10000 offset in SDRAM
      which is likely to contain already loaded data.
      The patch saves the oob data and the ecc on the stack replacing
      the fixed address in RAM.

      Signed-off-by: Stefano Babic <sbabic@denx.de>
      CC: Ilya Yanok <yanok@emcraft.com>
      CC: Scott Wood <scottwood@freescale.com>
      CC: Tom Rini <tom.rini@gmail.com>
      CC: Simon Schwarz <simonschwarzcor@googlemail.com>
      CC: Wolfgang Denk <wd@denx.de>
      Signed-off-by: Scott Wood <scottwood@freescale.com>

While nand_spl is on its way out, in favor of spl, there are still
many boards using it, and conversions are gradual.  This allows us
to get rid of CONFIG_SYS_NAND_ECCSTEPS and CONFIG_SYS_NAND_ECCTOTAL now,
which would otherwise be likely to linger unreferenced after a conversion.

It also eliminates a temporary error in the hawkboard_nand build, since
the spl version of the patch removed ECCSTEPS/TOTAL from hawkboard.h, but
the spl conversion is pending (and may be merged via a different tree).

Signed-off-by: Scott Wood <scottwood@freescale.com>
2012-01-26 16:09:06 -06:00
Wolfgang Denk
25ddd1fb0a Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value
CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not
being able to use "sizeof(struct global_data)" in assembler files.
Recent experience has shown that manual synchronization is not
reliable enough.  This patch renames CONFIG_SYS_GBL_DATA_SIZE into
GENERATED_GBL_DATA_SIZE which gets automatically generated by the
asm-offsets tool.  In the result, all definitions of this value can be
deleted from the board config files.  We have to make sure that all
files that reference such data include the new <asm-offsets.h> file.

No other changes have been done yet, but it is obvious that similar
changes / simplifications can be done for other, related macro
definitions as well.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
2010-10-26 21:05:30 +02:00
Wolfgang Denk
553f09823c Rename CONFIG_SYS_INIT_RAM_END into CONFIG_SYS_INIT_RAM_SIZE
CONFIG_SYS_INIT_RAM_END was a misnomer as it suggests this might be
some end address; to make the meaning more clear we rename it into
CONFIG_SYS_INIT_RAM_SIZE

No other code changes are performed in this patch, only minor editing
of white space (due to the changed length) and the comments was done,
where noticed.

Note that the code for the PATI and cmi_mpc5xx board configurations
looks seriously broken.  Last known maintainers on Cc:

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Denis Peter <d.peter@mpl.ch>
Cc: Martin Winistoerfer <martinwinistoerfer@gmx.ch>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
2010-10-26 21:03:25 +02:00
Wolfgang Denk
2ae1824196 Makefile: move all Power Architecture boards into boards.cfg
Clean up Makefile, and drop a lot of the config.mk files on the way.

We now also automatically pick all boards that are listed in
boards.cfg (and with all configurations), so we can drop the redundant
entries from MAKEALL to avoid building these twice.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-10-18 22:12:04 +02:00
Wolfgang Denk
14d0a02a16 Rename TEXT_BASE into CONFIG_SYS_TEXT_BASE
The change is currently needed to be able to remove the board
configuration scripting from the top level Makefile and replace it by
a simple, table driven script.

Moving this configuration setting into the "CONFIG_*" name space is
also desirable because it is needed if we ever should move forward to
a Kconfig driven configuration system.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-10-18 22:07:10 +02:00
Wolfgang Denk
2e6e1772c0 Merge branch 'next' of /home/wd/git/u-boot/next
Conflicts:
	include/ppc4xx.h

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-09-28 23:30:47 +02:00
Stefan Roese
550650ddd0 ppc4xx: Use common NS16550 driver for PPC4xx UART
This patch removes the PPC4xx UART driver. Instead the common NS16550
driver is used, since all PPC4xx SoC's use this peripheral device.

The file 4xx_uart.c now only implements the UART clock calculation
function which also sets the SoC internal UART divisors.

All PPC4xx board config headers are changed to use this common NS16550
driver now.

Tested on these boards:
acadia, canyonlands, katmai, kilauea, sequoia, zeus

Signed-off-by: Stefan Roese <sr@denx.de>
2010-09-23 09:02:05 +02:00
Michael Zaidman
800eb09641 POST cleanup.
- Revives POST for blackfin arch;
- Removes redundant code:
     arch/blackfin/lib/post.c
     arch/powerpc/cpu/ppc4xx/commproc.c
     arch/powerpc/cpu/mpc512x/common.c
- fixes up the post_word_{load|store} usage.

Signed-off-by: Michael Zaidman <michael.zaidman@gmail.com>
Acked-by: Detlev Zundel <dzu@denx.de>
Tested-by: Anatolij Gustschin <agust@denx.de>

List of the maintainers of the affected by patch boards:
Cc: Stephan Linz <linz@li-pro.net>
Cc: Denis Peter <d.peter@mpl.ch>
Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Niklaus Giger <niklaus.giger@netstal.com>
Cc: Larry Johnson <lrj@acm.org>
Cc: Feng Kan <fkan@amcc.com>
2010-09-21 21:39:31 +02:00
Chris Zhang
559e2c87e4 Adds EHCI definitions to sequoia board configuration file.
Adds required definitions for EHCI support in sequoia configuration file.
But still keeps the OHCI as default driver.

Signed-off-by: Chris Zhang <chris@seamicro.com>
2010-01-09 10:27:21 +01:00
Stefan Roese
a760b02031 ppc4xx: Consolidate pci_pre_init() function
This patch removes the duplicted implementations of the pci_pre_init()
function by introducing a weak default function for it. This weak default
has a different implementation for some PPC variants. It can be
overridden by a board specific version.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-11-19 11:35:30 +01:00
Stefan Roese
cfc2587462 ppc4xx: Sequoia: Add chip_config command
This patch removes the Sequoia "bootstrap" command and replaces it
with the now common command "chip_config".

Please note that the patches with the dynamic PCI sync clock
configuration have to be applied, before this one should go in.
This is because Sequoia has 2 different bootstrap EEPROMs, and
the old bootstrap command configured different values depending
on the detected PCI async clock (33 vs. 66MHz). With the PCI sync
clock patches, this is not necessary anymore. The PCI sync clock
will be configured correctly on-the-fly now.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-10-23 16:05:11 +02:00
Stefan Roese
d873133f2b ppc4xx: Add Sequoia RAM-booting target
This patch adds another build target for the AMCC Sequoia PPC440EPx
eval board. This RAM-booting version is targeted for boards without
NOR FLASH (NAND booting) which need a possibility to initially
program their NAND FLASH. Using a JTAG debugger (e.g. BDI2000/3000)
configured to setup the SDRAM, this debugger can load this RAM-
booting image to the target address in SDRAM (in this case 0x1000000)
and start it there. Then U-Boot's standard NAND commands can be
used to program the NAND FLASH (e.g. "nand write ...").

Here the commands to load and start this image from the BDI2000:

440EPX>reset halt
440EPX>load 0x1000000 /tftpboot/sequoia/u-boot.bin
440EPX>go 0x1000000

Please note that this image automatically scans for an already
initialized SDRAM TLB (detected by EPN=0). This TLB will not be
cleared. This TLB doesn't need to be TLB #0, this RAM-booting
version will detect it and preserve it. So booting via BDI2000
will work and booting with a complete different TLB init via
U-Boot works as well.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-06-12 20:39:47 +02:00
Stefan Roese
9a929170be ppc4xx: Disable POST memory test on NAND-booting Sequoia
Don't run the memory POST on the NAND-booting version. It will
overwrite part of the U-Boot image which is already loaded from NAND
to SDRAM. We were just lucky that it booted at all with this SDRAM
test enabled.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-04-16 09:12:08 +02:00
Wolfgang Grandegger
6c869637fe NAND: rename NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS
This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and
changes the default from 8 to 1 for the legacy and the new MTD
NAND layer. This allows to remove all NAND_MAX_CHIPS definitions
in the board config files because none of the boards use multi
chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440
define

 #define NAND_MAX_CHIPS          CONFIG_SYS_MAX_NAND_DEVICE

but that's bogus and did not work anyhow.

Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-01-23 10:32:51 -06:00
Jean-Christophe PLAGNIOL-VILLARD
6d0f6bcf33 rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-18 21:54:03 +02:00
Peter Tyser
abbb90666d Remove unused CFG_EEPROM_PAGE_WRITE_ENABLE references
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2008-10-14 14:45:31 +02:00
Jean-Christophe PLAGNIOL-VILLARD
0e8d158664 rename CFG_ENV macros to CONFIG_ENV
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-09-10 22:48:06 +02:00
Jean-Christophe PLAGNIOL-VILLARD
5a1aceb068 rename CFG_ENV_IS_IN_FLASH in CONFIG_ENV_IS_IN_FLASH
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-09-10 22:48:04 +02:00
Jean-Christophe PLAGNIOL-VILLARD
51bfee1920 rename CFG_ENV_IS_IN_NAND in CONFIG_ENV_IS_IN_NAND
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-09-10 22:47:58 +02:00
Stefan Roese
3d4a746e2f ppc4xx: Increase image size for NAND boot target
This is needed since now with HUSH enabled (amcc-common.h) the image
read from NAND exceeds the previous limit.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-08-30 11:24:44 +02:00
Jean-Christophe PLAGNIOL-VILLARD
00b1883a4c drivers/mtd: Move conditional compilation to Makefile
rename CFG_FLASH_CFI_DRIVER to CONFIG_FLASH_CFI_DRIVER

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-08-13 01:40:42 +02:00
Steven A. Falco
eab1007334 ppc4xx: Sequoia has two UARTs in "4-pin" mode. Configure the GPIOs as per schematic.
The Sequoia board has two UARTs in "4-pin" mode. This patch modifies the GPIO
configuration to match the schematic, and also sets the SDR0_PFC1 register to
select the corresponding mode for the UARTs.

Signed-off-by: Steven A. Falco <sfalco@harris.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-08-07 12:06:18 +02:00
Stefan Roese
72675dc6c0 ppc4xx: Unify AMCC's board config files (part 3/3)
This patch series unifies the AMCC eval board ports by introducing
a common include header for all AMCC eval boards:

include/configs/amcc-common.h

This header now includes all common configuration options/defines which
are removed from the board specific headers.

The reason for this is ease of maintenance and unified look and feel
of all AMCC boards.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-06 15:55:21 +02:00
Wolfgang Denk
53677ef18e Big white-space cleanup.
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).

Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-05-21 00:14:08 +02:00
Stefan Roese
14f73ca679 ppc: Add CFG_MEM_TOP_HIDE option to hide memory area that doesn't get "touched"
If CFG_MEM_TOP_HIDE is defined in the board config header, this specified
memory area will get subtracted from the top (end) of ram and won't get
"touched" at all by U-Boot. By fixing up gd->ram_size the Linux kernel
should gets passed the now "corrected" memory size and won't touch it
either. This should work for arch/ppc and arch/powerpc. Only Linux board
ports in arch/powerpc with bootwrapper support, which recalculate the
memory size from the SDRAM controller setup, will have to get fixed
in Linux additionally.

This patch enables this config option on some PPC440EPx boards as a workaround
for the CHIP 11 errata. Here the description from the AMCC documentation:

CHIP_11: End of memory range area restricted access.
Category: 3

Overview:
The 440EPx DDR controller does not acknowledge any
transaction which is determined to be crossing over the
end-of-memory-range boundary, even if the starting address is
within valid memory space. Any such transaction from any PLB4
master will result in a PLB time-out on PLB4 bus.

Impact:
In case of such misaligned bursts, PLB4 masters will not
retrieve any data at all, just the available data up to the
end of memory, especially the 440 CPU. For example, if a CPU
instruction required an operand located in memory within the
last 7 words of memory, the DCU master would burst read 8
words to update the data cache and cross over the
end-of-memory-range boundary. Such a DCU read would not be
answered by the DDR controller, resulting in a PLB4 time-out
and ultimately in a Machine Check interrupt. The data would
be inaccessible to the CPU.

Workaround:
Forbid any application to access the last 256 bytes of DDR
memory. For example, make your operating system believe that
the last 256 bytes of DDR memory are absent. AMCC has a patch
that does this, available for Linux.

This patch sets CFG_MEM_TOP_HIDE for the following 440EPx boards:
lwmon5, korat, sequoia

The other remaining 440EPx board were intentionally not included
since it is not clear to me, if they use the end of ram for some
other purpose. This is unclear, since these boards have CONFIG_PRAM
defined and even comments like this:

PMC440.h:
/* esd expects pram at end of physical memory.
 * So no logbuffer at the moment.
 */

It is strongly recommended to not use the last 256 bytes on those
boards too. Patches from the board maintainers are welcome.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-27 10:12:07 +01:00
Stefan Roese
fc84a8495a ppc4xx: Sequoia: Add device tree (fdt) Linux booting default env variables
Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-07 08:01:43 +01:00
Detlev Zundel
d8ab58b212 Replace "run load; run update" with conditionalized "run load update".
The latter version stops when "run load" fails for whatever reasons
rendering the combination *a lot* more secure.

Signed-off-by: Detlev Zundel <dzu@denx.de>
2008-03-06 17:35:40 +01:00
Wolfgang Denk
32bf3d143a Fix quoting problem (preboot setting) in many board config files.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-03-03 12:37:53 +01:00
Anatolij Gustschin
bc77881247 ppc4xx: Support for ATI Radeon 9200 card on sequoia
Adds configuration option for ATI Radeon 9200 card
support to sequoia config file. If CONFIG_VIDEO
is enabled, TEXT_BASE should be changed to 0xFFF80000.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2008-02-22 15:51:08 +01:00
Larry Johnson
214398d9cb ppc4xx: Beautify configuration files for Sequoia and Korat boards
Signed-off-by: Larry Johnson <lrj@acm.org>
2008-02-16 06:38:55 +01:00
Niklaus Giger
4d332dbeb0 ppc4xx: Make Sequoia boot vxWorks
vxWorks expects in
TLB 0 a entry for the Machine Check interrupt
TLB 1 a entry for the RAM
TLB 2 a entry for the EBC
TLB 3 a entry for the boot flash

After changing the baudrate to 9600 I had no problems to boot the
vxWorks image as distributed by WindRiver (Revision 2.0/1 from
June 18, 2007)

Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
2008-01-10 19:06:54 +01:00
Lawrence R. Johnson
b05e8bf58b ppc4xx: Use CFG_4xx_GPIO_TABLE to configure Sequoia board
Note: this patch changes the configuration of some GPIO registers:

   Register      Old Value   New Value
---------------  ----------  ----------
DCR GPIO0_TCR    0x0000000F  0x0000F0CF
DCR GPIO0_TSRH   0x55005000  0x00000000
DCR GPIO1_TCR    0xC2000000  0xE2000000
DCR GPIO1_TSRL   0x0C000000  0x00200000
DCR GPIO1_ISR2L  0x00050000  0x00110000

Signed-off-by: Larry Johnson <lrj@acm.org>
2008-01-04 11:39:05 +01:00
Stefan Roese
42d55ea0bd ppc4xx: Move virtual address of POST cache test to bigger address
On Sequoia & LWMON5 the virtual address of the POST cache test is now
moved to a bigger address. This enables usage of more memory on those
boards.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-12-27 19:35:35 +01:00
Stefan Roese
328a340392 ppc4xx: fdt: Cleanup setup of cpu node setup
Now the cpu node setup ("timebase-frequency" and "clock-frequency") is
without using the absolute path to the cpu node. This makes it possible
to use this U-Boot version with both versions of cpu-node naming
"cpu@0" and the former "PowerPC,440EPx@0".

Signed-off-by: Stefan Roese <sr@denx.de>
2007-12-27 19:35:34 +01:00
Markus Klotzbücher
052440b022 ppc4xx: Add CONFIG_BOOTP_SUBNETMASK to Sequoia board config
When using dhcp/bootp the "netmask" environment variable is not
set because CONFIG_BOOTP_SUBNETMASK is not defined. But usually this is
desireable, so the following patch adds this this option to the board
config.

Signed-off-by: Markus Klotzbuecher <mk@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-12-27 19:35:33 +01:00
Stefan Roese
136288847e ppc4xx: Bring 4xx fdt support up-to-date
This patch update the 4xx fdt support. It enabled fdt booting
on the AMCC Kilauea and Sequoia for now. More can follow later
quite easily.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-12-27 19:35:32 +01:00
Matthias Fuchs
2d14684341 ppc4xx: Use generic usb-ohci driver for sequoia board
This patch makes the sequoia board use the generic usb-ohci driver
instead of cpu/ppc4xx/usb_ohci.c.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-11-09 16:42:15 +01:00
Stefan Roese
d25dfe08fb ppc4xx: Remove cache definition from 4xx board config files
All 4xx board config files don't need the cache definitions anymore.
These are now defined in common headers.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:47 +01:00
Stefan Roese
5a5958b7de ppc4xx: Fix incorrect 33/66MHz PCI clock log-message on Sequoia & Yosemite
The BCSR status bit for the 66MHz PCI operation was correctly
addressed (MSB/LSB problem). Now the correct currently setup
PCI frequency is displayed upon bootup.

This patch also fixes this problem on Rainier & Yellowstone, since these
boards use the same souce code as Sequoia & Yosemite do.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-15 11:29:33 +02:00
Gary Jennejohn
81b73dec16 ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx Sequoia
The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is
set to non-zero, because it doesn't support MRM (memory-read-
multiple) correctly. We now added the possibility to configure
this register in the board config file, so that the default value
of 8 can be overridden.

Here the details of this patch:

o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow
  board-specific settings. As an example the sequoia board requires 0.
  Idea from Stefan Roese <sr@denx.de>.
o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the
  PCI IO-space. Obtained from Stefan Roese <sr@denx.de>.
o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set
  CFG_PCI_CACHE_LINE_SIZE to 0.

Signed-off-by: Gary Jennejohn <garyj@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-08-31 15:21:46 +02:00
Stefan Roese
9de469bd96 ppc4xx: Only enable POST FPU test on Sequoia and not Rainier
Signed-off-by: Stefan Roese <sr@denx.de>
2007-08-16 10:18:33 +02:00
Andy Fleming
6bf6f114dc Merge branch 'testing' into working
Conflicts:

	CHANGELOG
	fs/fat/fat.c
	include/configs/MPC8560ADS.h
	include/configs/pcs440ep.h
	net/eth.c
2007-08-03 02:23:23 -05:00
Jon Loeliger
079a136c35 include/configs/[p-z]* + misc: Cleanup BOOTP and lingering CFG_CMD_*.
Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h
used to be included but CONFIG_BOOTP_MASK was not defined.

Remove lingering references to CFG_CMD_* symbols.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-07-10 10:12:10 -05:00
Jon Loeliger
46da1e96b7 include/configs: Use new CONFIG_CMD_* in various s* named board config files.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-07-05 11:05:13 +02:00
Sergei Poselenov
b44896215a Merged POST framework with the current TOT.
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
2007-07-05 08:17:37 +02:00
Stefan Roese
e4feb7638c Merge with git://www.denx.de/git/u-boot.git 2007-06-25 20:20:30 +02:00
Stefan Roese
466fff1a7b ppc4xx: Add pci_pre_init() for 405 boards
This patch removes the CFG_PCI_PRE_INIT option completely, since
it's not needed anymore with the patch from Matthias Fuchs with
the "weak" pci_pre_init() implementation.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-25 15:57:39 +02:00
Wolfgang Denk
1636d1c852 Coding stylke cleanup; rebuild CHANGELOG 2007-06-22 23:59:00 +02:00
Igor Lisitsin
a11e06965e Extend POST support for PPC440
Added memory, CPU, UART, I2C and SPR POST tests for PPC440.

Signed-off-by: Igor Lisitsin <igor@emcraft.com>
--
2007-06-22 23:21:01 +02:00
Grzegorz Bernacki
efa35cf12d ppc4xx: Clean up 440 exceptions handling
- Introduced dedicated switches for building 440 and 405 images required
  for 440-specific machine instructions like 'rfmci' etc.

- Exception vectors moved to the proper location (_start moved away from
  the critical exception handler space, which it occupied)

- CriticalInput now serviced (with default handler)

- MachineCheck properly serviced (added a dedicated handler and return
  subroutine)

- Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused,
  unhandled and those not relevant for 4xx were eliminated)

- Eliminated Linux leftovers, removed dead code

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-15 11:19:28 +02:00