Commit graph

1724 commits

Author SHA1 Message Date
Nick Spence
3924384060 mpc86xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cache
This is needed in unlock_ram_in_cache() because it is called from C and
will corrupt the small data area anchor that is kept in R2.

lock_ram_in_cache() is modified similarly as good coding practice, but
is not called from C.

Signed-off-by: Nick Spence <nick.spence@freescale.com>
2008-10-13 13:57:14 +02:00
Kumar Gala
5c7cbcd34d 86xx: remove redudant code with lib_ppc/interrupts.c
For some reason we duplicated the majority of code in lib_ppc/interrupts.c
Not know how that happened, but there is no good reason for it.

Use the interrupt_init_cpu() and timer_interrupt_cpu() since its why
they exist.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-13 13:56:18 +02:00
Stefan Roese
1f6aa622e3 Merge branch 'master' of /home/stefan/git/u-boot/u-boot 2008-10-13 11:17:31 +02:00
Wolfgang Denk
22a871a464 Merge branch 'master' of git://git.denx.de/u-boot-arm 2008-10-12 23:55:12 +02:00
Wolfgang Denk
1f7bab0832 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2008-10-12 23:12:44 +02:00
Wolfgang Grandegger
dffd2446fb 85xx: Using proper I2C source clock divider for MPC8544
Measurements with our MPC8544 board showed that the I2C bus frequency
is wrong by a factor of 1.5. Obviously, the interpretation of the
MPC85xx_PORDEVSR2_SEC_CFG bit of the cfg_sec_freq register is not
correct. There seems to be an error in the 8544 RM.

Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
2008-10-08 14:20:27 -05:00
Guennadi Liakhovetski
1ed7a7f0f5 i.MX31: switch to CFG_HZ=1000
Switch to the standard CFG_HZ=1000 value, while at it, minor white-space
cleanup, remove CFG_CLKS_IN_HZ from config-headers. Tested on mx31ads,
provides 2% or 0.4% precision depending on the
CONFIG_MX31_TIMER_HIGH_PRECISION flag. Measured with stop-watch on 100s
boot-delay.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
2008-10-08 18:59:02 +02:00
Adam Graham
f8a00dea84 ppc4xx: Reset and relock memory DLL after SDRAM_CLKTR change
After changing SDRAM_CLKTR phase value rerun the memory preload
initialization sequence (INITPLR) to reset and relock the memory
DLL. Changing the SDRAM_CLKTR memory clock phase coarse timing
adjustment effects the phase relationship of the internal, to the
PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT.

Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-08 11:36:23 +02:00
Jason Jin
c0391111c3 Fix the incorrect DDR clk freq reporting on 8536DS
On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111),
The display is still sync mode DDR freq. This patch try to fix
this. The display DDR freq is now the actual freq in both
sync and async mode.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2008-10-07 15:37:08 -05:00
Kumar Gala
bac6a1d1fa 85xx: Remove setting of *cache-line-size in device trees
ePAPR says if the *cache-block-size is the same as *cache-line-size
than we don't need the *cache-line-size property.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-07 10:28:59 -05:00
Anton Vorontsov
d26154c9a6 mpc83xx: spd_sdram: fix ddr sdram base address assignment bug
The spd_dram code shifts the base address, then masks 20 bits, but
forgets to shift the base address back. Fix this by just masking the
base address correctly.

Found this bug while trying to relocate a DDR memory at the base != 0.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-09-24 09:58:33 -05:00
Wolfgang Denk
5fdc215f0b Fix DPRAM memory leak when CFG_ALLOC_DPRAM is defined, which
eventually leads to a machine check. This change assures that DPRAM
is allocated only once in that case.

Signed-off-by: Gary Jennejohn <garyj@denx.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-09-22 22:23:06 +02:00
Nobuhiro Iwamatsu
4a065abf92 sh: Add support watchdog for SH4A core
Add support watchdog for SH4A core (SH7763, SH7780 and SH7785).
And fix some compile warning.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-09-19 11:05:22 +09:00
Wolfgang Denk
f12e4549b6 Coding style cleanup, update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-09-13 02:23:05 +02:00
Wolfgang Denk
508eb85db7 Merge branch 'master' of git://git.denx.de/u-boot-nand-flash 2008-09-13 01:45:56 +02:00
Wolfgang Denk
afbc526336 Merge branch 'Makefile-next' of git://git.denx.de/u-boot-arm 2008-09-12 16:13:12 +02:00
Wolfgang Denk
b476b03256 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2008-09-12 15:23:20 +02:00
Stefan Roese
7bf5ecfa50 ppc4xx: Fix SDRAM inititialization of multiple 405 based board ports
This patch fixes a problem introdiced with patch
bbeff30c [ppc4xx: Remove superfluous dram_init() call or replace it by
initdram()].

The boards affected are:
- PCI405
- PPChameleonEVB
- quad100hd
- taihu
- zeus

Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-12 07:12:33 +02:00
Jens Scharsig
3ee9f03f58 at91rm9200: fix errors with CONFIG_CMD_I2C_TREE
This patch prevents linker error on AT91RM9200 boards, if
CONFIG_CMD_I2_TREE is set.
It implements i2c_set_bus_speed and i2c_get_bus_speed as a dummy function.

Signed-off-by: Jens Scharsig <esw@bus-elektronik.de>
2008-09-12 02:20:47 +02:00
Hugo Villeneuve
b5b0344957 ARM DaVinci: Remove duplicate code in cpu/arm926ejs/davinci/dp83848.c
ARM DaVinci: Remove duplicate code in cpu/arm926ejs/davinci/dp83848.c

Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
2008-09-12 02:20:47 +02:00
Andrew Dyer
274737e5eb i.mx change get_timer(base) to return time since base
This patch changes get_timer() for i.MX to return the time since
'base' instead of the time since the counter was at zero.

Symptom seen is flash timeout errors when erasing or programming a
sector using the common cfi flash code.

Signed-off-by: Andrew Dyer <adyer@righthandtech.com>
2008-09-12 02:20:46 +02:00
Andrew Dyer
48fed40575 i.MX use u-boot baud rate and don't assume UART master clock
1) Change the i.MX serial driver to use the baud rate set in the
 u-boot environment

2) don't assume a 16MHz value for PERCLK1 in baud rate calculations

3) don't write a 1 to the RDR bit in the USR2 reg. (bit is not "write
 one to clear" like other status bits in the reg.)

Signed-off-by: Andrew Dyer <adyer@righthandtech.com>
2008-09-12 02:20:46 +02:00
Andrew Dyer
6e1551a870 arm920t fix constant error in start.S
Code in cpu/arm920t/start.S will die with a compilation error if
CONFIG_STACKSIZE + CFG_MALLOC_LEN works out to an invalid constant for
the ARM sub instruction.  Change the code so that each is subtracted
independently to avoid the error.

Signed-off-by: Andrew Dyer <adyer@righthandtech.com>
2008-09-12 02:20:46 +02:00
Adrian Filipi
c455d07396 Set up SD/MMC OCR as comment describes. i.e. 3.2-3.4v.
Signed-off-by: Adrian Filipi <adrian.filipi@eurotech.com>
2008-09-12 01:23:44 +02:00
Magnus Lilja
8c4ebec25b i.MX31: Add reset_timer() and modify get_timer_masked().
This patch adds the reset_timer() function (needed by nand_base.c) and
modifies the get_timer_masked() to work in the same way as the omap24xx
function.

Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
2008-09-12 01:23:43 +02:00
Jean-Christophe PLAGNIOL-VILLARD
0cf4fd3cf8 rename environment.c in env_embedded.c to reflect is functionality
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-09-10 22:48:01 +02:00
Jean-Christophe PLAGNIOL-VILLARD
9314cee691 rename CFG_ENV_IS_IN_NVRAM in CONFIG_ENV_IS_IN_NVRAM
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-09-10 22:47:59 +02:00
Hugo Villeneuve
9b05aa788b ARM DaVinci: Fix broken HW ECC for large page NAND.
Based on original patch by Bernard Blackham <bernard@largestprime.net>

U-boot's HW ECC support for large page NAND on Davinci is completely
broken.  Some kernels, such as the 2.6.10 one supported by
MontaVista for DaVinci, rely upon this broken behaviour as they
share the same code for ECCs. In the existing scheme, error
detection *might* work on large page, but error correction
definitely does not.  Small page ECC correction works, but the
format is not compatible with the mainline git kernel.

This patch adds ECC code that matches what is currently in the
Davinci git repository (since NAND support was added in 2.6.24).
This makes the ECC and OOB layout written by u-boot compatible with
Linux for both small page and large page devices and fixes ECC
correction for large page devices.

The old behaviour can be restored by defining the macro
CFG_DAVINCI_BROKEN_ECC, which is undefined by default.

Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
Acked-by: Sergey Kubushyn <ksi@koi8.net>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-09-10 11:40:30 -05:00
Andrew Klossner
5251469943 Fix printf errors under -DDEBUG
Fix printf format-string/arg mismatches under -DDEBUG.

These warnings occur with DEBUG defined for a platform using
cpu/mpc85xx.  Users of other architectures can unearth similar
problems by adding the line "CFLAGS += -DDEBUG=1" in config.mk right
after "CFLAGS += $(call cc-option,-fno-stack-protector)".

Signed-off-by: Andrew Klossner <andrew@cesa.opbu.xerox.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-09-09 17:02:41 -05:00
Kumar Gala
e0ff3d350d 85xx: Ensure timebase is zero on secondary cores
The e500um says the timebase is volatile out of reset.  To ensure
TB sync works we need to make sure its zero.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-09-09 16:52:45 -05:00
Sergei Poselenov
59f630588e Removed hardcoded MxMR loop value from upmconfig() for MPC85xx.
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
2008-09-09 10:14:32 +02:00
Wolfgang Denk
ab00e7a23e Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
Conflicts:

	Makefile

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-09-09 02:24:51 +02:00
Sergei Poselenov
1bb8b2ef27 ARM: fix warning: target CPU does not support interworking
This patch fixes warnings like this:

start.S:0: warning: target CPU does not support interworking

which come from some ARM cross compilers and are caused by hard-coded
(with "--with-cpu=arm9" configuration option) ARM targets (which
support ARM Thumb instructions), while the ARM target selected from
the command line (with "-march=armv4") doesn't support Thumb
instructions.

This warning is issued by the compiler regardless of the real use of
the Thumb instructions in code.

To fix this problem, we use options according to compiler version
being used.

Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-09-09 02:14:43 +02:00
Sergei Poselenov
4265c35fbc ARM: Use do_div() instead of division for "long long".
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-09-09 02:14:41 +02:00
Stefan Roese
c351575c22 Merge branch 'master' of /home/stefan/git/u-boot/u-boot 2008-09-08 10:35:49 +02:00
Stefan Roese
f071f01fd0 ppc4xx: Remove CONFIG_CS8952_PHY define
Since this define is only used on one board that was never really in
production, removing this compile time option doesn't hurt and makes
the code more readable.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-08 10:27:56 +02:00
Stefan Roese
6ca8646c18 ppc4xx: Fix compilation warning for PIP405
This patch fixes a compilation warning for the PIP405 board. It moves the
#ifndef CONFIG_CS8952_PHY define a little so that the warning doesn't
occur anymore. I am a little unsure if this #ifdef is at the correct
place now or if it could be removed completely. This needs to get
tested on the PIP405 board.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-08 10:27:51 +02:00
Stefan Roese
725b53ac61 ppc4xx: Fix compilation warning for canyonlands & glacier
Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-08 10:27:46 +02:00
Kumar Gala
302e52e0b1 Fix compiler warning in mpc8xxx ddr code
ctrl_regs.c: In function 'compute_fsl_memctl_config_regs':
ctrl_regs.c:523: warning: 'caslat' may be used uninitialized in this function
ctrl_regs.c:523: note: 'caslat' was declared here

Add a warning in DDR1 case if cas_latency isn't a value we know about.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-09-07 01:26:13 +02:00
Jean-Christophe PLAGNIOL-VILLARD
d1e2319414 rtc: allow rtc_set to return an error and use it in cmd_date
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-09-07 00:56:36 +02:00
Victor Gallardo
78d7823689 ppc4xx: Add support for GPCS, SGMII and M88E1112 PHY
This patch adds GPCS, SGMII and M88E1112 PHY support
for the AMCC PPC460GT/EX processors.

Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-05 12:21:16 +02:00
Adam Graham
f6b6c45840 ppc4xx: Update Kilauea to use PPC4xx DDR autocalibration routines
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-05 12:04:16 +02:00
Adam Graham
075d0b81e8 ppc4xx: IBM Memory Controller DDR autocalibration routines
Alternate SDRAM DDR autocalibration routine that can be generically used
for any PPC4xx chips that have the IBM SDRAM Controller core allowing for
support of more DIMM/memory chip vendors and gets the DDR autocalibration
values which give the best read latency performance (SDRAM0_RDCC.[RDSS]).

Two alternate SDRAM DDR autocalibration algoritm are provided in this patch,
"Method_A" and "Method_B".  DDR autocalibration Method_A scans the full range
of possible PPC4xx  SDRAM Controller DDR autocalibration values and takes a
lot longer to run than Method_B.  Method_B executes in the same amount of time
as the currently existing DDR autocalibration routine, i.e. 1 second or so.
Normally Method_B is used and it is set as the default method.

The current U-Boot PPC4xx DDR autocalibration code calibrates the IBM SDRAM
Controller registers.[bit-field]:
1)  SDRAM0_RQDC.[RQFD]
2)  SDRAM0_RFDC.[RFFD]

This alternate PPC4xx DDR autocalibration code calibrates the following
IBM SDRAM Controller registers.[bit-field]:

1)  SDRAM0_WRDTR.[WDTR]
2)  SDRAM0_CLKTR.[CKTR]
3)  SDRAM0_RQDC.[RQFD]
4)  SDRAM0_RFDC.[RFFD]

and will also use the calibrated settings of the above four registers that
produce the best "Read Sample Cycle Select" value in the SDRAM0_RDCC.[RDSS]
register.[bit-field].

Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-05 12:03:44 +02:00
Wolfgang Denk
d459516188 Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx 2008-09-03 23:44:18 +02:00
Nick Spence
6eb2a44e27 mpc83xx: clean up cache operations and unlock_ram_in_cache() functions
Cleans up some latent issues with the data cache control so that
dcache_enable() and dcache_disable() will work reliably (after
unlock_ram_in_cache() has been called)

Signed-off-by: Nick Spence <nick.spence@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-09-03 16:07:00 -05:00
Nick Spence
46497056ae mpc83xx: Store and display Arbiter Event Register values
Record the Arbiter Event Register values and optionally display them.

The Arbiter Event Register can record the type and effective address of
an arbiter error, even through an HRESET. This patch stores the values in
the global data structure.

Display of the Arbiter Event registers immediately after the RSR value
can be enabled with defines. The Arbiter values will only be displayed
if an arbiter event has occured since the last Power On Reset, and either
of the following defines exist:
 #define CONFIG_DISPLAY_AER_BRIEF - display only the arbiter address and
                                    and type register values
 #define CONFIG_DISPLAY_AER_FULL  - display and interpret the arbiter
                                    event register values

Address Only transactions are one of the trapped events that can register
as an arbiter event. They occur with some cache manipulation instructions
if the HID0_ABE (Address Broadcast Enable) is set and the memory region
has the MEMORY_COHERENCE WIMG bit set. Setting:
 #define CONFIG_MASK_AER_AO - prevents the arbiter from recording address
                              only events, so that it can still capture
                              other real problems.

Signed-off-by: Nick Spence <nick.spence@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-09-03 16:06:57 -05:00
Nick Spence
ade50c7fa1 mpc83xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cache
This is needed in unlock_ram_in_cache() because it is called from C and
will corrupt the small data area anchor that is kept in R2.

lock_ram_in_cache() is modified similarly as good coding practice, but
is not called from C.

Signed-off-by: Nick Spence <nick.spence@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-09-03 16:06:51 -05:00
Nick Spence
d9fe88173c MPC83XX: Fix GPIO configuration - set gpio level before direction
Set DAT value before DIR values to avoid creating glitches on the
GPIO signals.

Set gpio level register before direction register to inhibit
glitches on high level output pins.

Dir and data gets cleared at powerup, so high level output lines see
a short low pulse between setting the direction and level registers.

Issue was seen on a new board with the nReset line of the NOR flash
connected to a GPIO. Setting the direction register puts the NOR flash
in reset so the next instruction to set the level cannot get executed.

Signed-off-by: Nick Spence <nick.spence@freescale.com>
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-09-03 16:06:46 -05:00
Ben Warren
e1d7480b5d Moved initialization of MPC5xxx_FEC Ethernet driver to CPU directory
Modified board_eth_init() functions of boards that have this FEC in addition
to other Ethernet controllers.

Affected boards:
	bc3450
	icecube
	mvbc_p
	o2dnt
	pm520
	total5200
	tq5200

Removed initialization of controller from net/eth.c

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-09-02 21:18:18 -07:00
Ben Warren
a0aad08f94 Moved initialization of MPC512x_FEC Ethernet driver to CPU directory
Added a cpu_eth_init() function to MPC512x CPU directory and
removed code from net/eth.c

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-09-02 21:18:17 -07:00