Commit graph

13 commits

Author SHA1 Message Date
J. German Rivera
7b3bd9a798 drivers/mc: Migrated MC Flibs to 0.5.2
Upgrade Manage Complex (MC) flib API to 0.5.2. Rename directory
fsl_mc to fsl-mc. Change the fsl-mc node in Linux device tree
from "fsl,dprcr" to "fsl-mc". Print MC version info when
appropriate.

Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-02-24 13:10:20 -08:00
Bhupesh Sharma
bbeeb8bec0 ls2085/configs: Ensure right banners are printed for EMU and SIMU
This patch enusres that right banners are printed for LS2085A
emulator and simulator platforms.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-02-24 13:10:02 -08:00
Stuart Yoder
052ddd5c81 ARMv8/ls2085a: Move kernel image load address
Move the load address of the kernel image to get it away from the
region of the uncompressed kernel.

Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-02-24 13:09:56 -08:00
Arnab Basu
40e61f8e54 ARMv8/ls2085a: Switch to passing earlycon to kernel
Since Linux v3.16-rc1 earlyprintk has been removed for arm64.
Switch to using earlycon.

Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24 13:09:52 -08:00
York Sun
064d031ca6 ARMv8/LS2085A: Adjust system clock and DDR clock
Set system clock to 100MHz and DDR clock to 133MHz.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24 13:09:36 -08:00
Kuldip Giroh
27f277fe33 ARMv8/LS2085A: HugeTLB support is required by default in LS NADK
LS NADK memory manager by default works on HugeTLB. Hence bootargs
must include parameters default_hugepagesz (default hugepagesize,
hugepagesz (hugepage size) and hugepages (number of hugepages to be
reserved in kernel for the given size).

Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-02-24 13:09:30 -08:00
Bhupesh Sharma
9c66ce662c fsl-ch3/lowlevel: TZPC and TZASC programming to configure non-secure accesses
This patch ensures that the TZPC (BP147) and TZASC-400 programming
happens for LS2085A SoC only when the desired config flags are
enabled and ensures that the TZPC programming is done to allow Non-secure
(NS) + secure (S) transactions only for DCGF registers.

The TZASC component is not present on LS2085A-Rev1, so the TZASC-400
config flag is turned OFF for now.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-02-24 13:08:06 -08:00
Masahiro Yamada
8c688bc4de kconfig: move CONFIG_SYS_HZ to lib/Kconfig
CONFIG_SYS_HZ is always defined as 1000 in config_fallbacks.h
(but some boards still have redundant definitions).

This commit moves the definition and the document in README to
Kconfig.  Since lib/Kconfig can assure that CONFIG_SYS_HZ is 1000,
the sanity check in lib/time.c should be removed.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2014-10-23 13:18:59 -04:00
York Sun
8aeb893a8e ARMv8/ls2085a: Move u-boot location to make room for RCW
When booting with SP, RCW resides at the beginning of IFC NOR flash.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-25 08:36:19 -07:00
York Sun
8bfa301b0a ARMv8/ls2085a: Enable secondary cores
Spin table is at the very beginning of boot code. Each core has an individual
release address within the spin table, the ft_cpu_setup fn updates the
"cpu-release-addr" property of each cpu node with the corresponding release
address.

Also fix CPU_RELEASE_ADDR to point to secondary_boot_func.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-09-25 08:36:19 -07:00
York Sun
d9c68b1444 ARMv8/ls2085a_emu: Enable DP-DDR as standalone memory block
DP-DDR is used for DPAA, separated from main memory pool for general
use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit).

Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-25 08:36:18 -07:00
Prabhakar Kushwaha
e211c12e77 board/ls2085a: Add support of NOR and NAND flash for simulator
Add support of NOR and NAND flash for simulator target.
Here
  IFC - CS0: NOR flash
  IFC - CS1: NAND flash

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-09-25 08:36:17 -07:00
York Sun
f749db3a75 ARMv8/ls2085a_emu: Add LS2085A emulator and simulator board support
LS2085A is an ARMv8 implementation. This adds board support for emulator
and simulator:
  Two DDR controllers
  UART2 is used as the console
  IFC timing is tightened for speedy booting
  Support DDR3 and DDR4 as separated targets
  Management Complex (MC) is enabled
  Support for GIC 500 (based on GICv3 arch)

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
2014-07-04 19:48:41 +02:00