Commit graph

891 commits

Author SHA1 Message Date
Wolfgang Denk
aef293bc85 Merge branch 'phylib' of git://git.denx.de/u-boot-mmc 2011-04-20 23:01:52 +02:00
Wolfgang Denk
9dd5dad887 Merge branch 'misc' of git://git.denx.de/u-boot-blackfin 2011-04-20 22:57:35 +02:00
Wolfgang Denk
8c4734e9af Revert "PowerPC: Add support for -msingle-pic-base"
This reverts commit 39768f7715.

Reson: it breaks a number of boards with embedded environment as the
code size grows in some places.
2011-04-20 22:11:21 +02:00
Andy Fleming
865ff85640 fsl: Change fsl_phy_enet_if to phy_interface_t
The fsl_phy_enet_if enum was, essentially, the phy_interface_t enum.
This meant that drivers which used fsl_phy_enet_if to deal with
PHY interfaces would have to convert between the two (or we would have
to have them mirror each other, and deal with the ensuing maintenance
headache). Instead, we switch all clients of fsl_phy_enet_if over to
phy_interface_t, which should become the standard, anyway.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-20 15:09:35 -05:00
Andy Fleming
063c12633d tsec: Convert tsec to use PHY Lib
This converts tsec to use the new PHY Lib.  All of the old PHY support
is ripped out.  The old MDIO driver is split off, and placed in
fsl_mdio.c.  The initialization is modified to initialize the MDIO
driver as well.  The powerpc config file is modified to configure PHYLIB
if TSEC_ENET is configured.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-20 15:09:34 -05:00
Mike Frysinger
a972b8d701 gpio: generalize for all generic gpio providers
The Blackfin gpio command isn't terribly Blackfin-specific.  So generalize
the few pieces into two new optional helpers:
	name_to_gpio() - turn a string name into a GPIO #
	gpio_status() - display current pin bindings (think /proc/gpio)

Once these pieces are pulled out, we can relocate the cmd_gpio.c into the
common directory.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-13 15:56:51 -04:00
Graeme Russ
b7af583185 sc520: Move reset to stand-alone file
Partial linking allows weak functions to be overridden in files containing
only one function. Moving the sc520 override of reset_cpu gets rid of an
ugly #ifdef

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2011-04-13 19:43:29 +10:00
Graeme Russ
fea2572001 x86: Rename i386 to x86
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2011-04-13 19:43:28 +10:00
Graeme Russ
dbf7115a32 x86: Code cleanup
Make the copyright notices in the x86 files consistent and update them with
proper attributions for recent updates

Also fix a few comment style/accuracy and whitespace/blank line issues

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2011-04-13 19:43:26 +10:00
Graeme Russ
e413554f9d eNET: Remove config.mk
By including <config.h> in the ld script, CONFIG_SYS_MONITOR_LEN (defined
in the boards config file) can be used in lieu of FLASH_SIZE (defined in
the board specific config.mk)

As this is the last remaining entry in the board specific config.mk, this
file can now be removed

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2011-04-13 19:43:25 +10:00
Wolfgang Denk
8ae86b76c6 Make STANDALONE_LOAD_ADDR configurable per board
Rename STANDALONE_LOAD_ADDR into CONFIG_STANDALONE_LOAD_ADDR
and allow that the architecture-specific default value gets
overwritten by defining the value in the board header file.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Cc: Daniel Hellstrom <daniel@gaisler.com>
Cc: Tsi Chung Liew <tsi-chung.liew@freescale.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2011-04-12 22:58:32 +02:00
Loïc Minier
6052cbab40 Fix misc spelling errors found by lintian
Signed-off-by: Loc Minier <loic.minier@linaro.org>
2011-04-12 22:58:31 +02:00
Joakim Tjernlund
39768f7715 PowerPC: Add support for -msingle-pic-base
-msingle-pic-base is a new gcc option for ppc and
it reduces the size of my u-boot with 6-8 KB.
While at it, add -fno-jump-tables too to save a
few more bytes.

-msingle-pic-base will be in gcc 4.6, however
backported patches are available at
http://bugs.gentoo.org/show_bug.cgi?id=347281

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
2011-04-11 21:38:47 +02:00
Joakim Tjernlund
33ee4c9233 PowerPC: Move -fPIC flag to common place
The -fPIC flag belongs with -mrelocatable, move it there.
Also change -fPIC to -fpic as this produces smaller
binaries.
However, currently -mrelocatable promotes -fpic to -fPIC, a
fix for this is in upcoming gcc 4.6 or you can apply this small
patch to gcc:

diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h
index 8da8410..e4b8280 100644
--- a/gcc/config/rs6000/sysv4.h
+++ b/gcc/config/rs6000/sysv4.h
@@ -227,7 +227,8 @@ do {									\
     }									\
 									\
   else if (TARGET_RELOCATABLE)						\
-    flag_pic = 2;							\
+    if (!flag_pic)							\
+      flag_pic = 2;							\
 } while (0)

 #ifndef RS6000_BI_ARCH
--

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
2011-04-11 21:36:41 +02:00
Wolfgang Denk
17e967b3df Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2011-04-10 21:24:40 +02:00
Fabian Cenedese
c1c087b753 powerpc/85xx: Removed clearing of L2-as-SRAM
Removed clearing of L2 cache as SRAM as it is not necessary without ECC.
This also speeds up the booting process.

Signed-off-by: Fabian Cenedese <cenedese@indel.ch>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-10 11:24:21 -05:00
Priyanka Jain
32c8cfb23c fsl_esdhc: Deal with watermark level register related changes
P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark
level register description has been changed:

9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00
25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-10 11:17:55 -05:00
Shaohui Xie
2a9fab82b7 powerpc/85xx: Add PBL boot from SPI flash support on P4080DS
PBL(pre-boot loader): SPI flash used as RCW(Reset Configuration Word) and
PBI(pre-boot initialization) source, CPC(CoreNet Platform Cache) used as
1M SRAM where PBL will copy whole U-BOOT image to, U-boot can boot from
CPC after PBL completes RCW and PBI phases.

Signed-off-by: Chunhe Lan <b25806@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-10 11:17:55 -05:00
Jiang Yutang
b93f81a418 powerpc/85xx: Add support usb2/etsec and tdm/audio pin multiplex on P1022DS
For soc which have pin multiplex relation, some of them can't enable
simultaneously. This patch add environment var 'hwconfig' content
defination for them. you can enable some one function by setting
environment var 'hwconfig' content and reset board. Detail setting
please refer doc/README.p1022ds

Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-10 11:17:55 -05:00
Timur Tabi
314b3ff1a6 p4080ds: remove rev1-specific code for the SERDES8 erratum
Remove the SERDES8 erratum work-around code that only applied to P4080
rev1, which is not supported by this version of U-Boot.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-10 11:17:48 -05:00
Matthew McClintock
a3055c587d powerpc/85xx: rename NAND prefixes to CONFIG_SYS
renaming 85xx define CONFIG_NAND_OR_PRELIM to CONFIG_SYS_NAND_OR_PRELIM
and CONFIG_NAND_BR_PRELIM to CONFIG_SYS_NAND_BR_PRELIM to use the more
appropriate CONFIG_SYS prefix as well as be consistent with 83xx.

Signed-off-by: Matthew McClintock <msm@freescale.com>
cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-08 02:50:57 -05:00
Kyle Moffett
eed1a7b1cf Blackfin: replace "bfin_reset_or_hang()" with "panic()"
The bfin_reset_or_hang function unnecessarily duplicates the panic()
logic based on CONFIG_PANIC_HANG.

This patch deletes 20 lines of code and just calls panic() instead.
This also makes the following generic-restart conversion patch simpler.

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-08 00:44:27 -04:00
Mike Frysinger
e8065f8889 Blackfin: bootrom.h: sync with toolchain
We need the updated LDR bit defines for our LDR utils.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-08 00:44:27 -04:00
Mike Frysinger
105be9078c Blackfin: default to L1 bank A when L1 bank B does not exist
Some parts lack Bank B in L1 data, so have the linker script fall back to
Bank A when that happens.  This way we can still leverage L1 data.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-08 00:44:26 -04:00
Mike Frysinger
c745a84648 Blackfin: turn off caches when self initializing
When bootstrapping ourselves on the fly at runtime (via "go"), we need to
turn off the caches to avoid taking software exceptions.  Since caches
need CPLBs and CPLBs need exception handlers, but we're about to rewrite
the code in memory where those exception handlers live, we need to turn
off caches first.

This new code also encourages a slight code optimization by storing the
MMR bases in dedicated registers so we don't have to fully load up the
pointer regs multiple times.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-08 00:44:26 -04:00
Mike Frysinger
05e7825e49 Blackfin: only check for os log when we have external memory
If the part has no external memory configured, then there will be no os
log for us to check, and any attempt to access that memory will trigger
hardware errors.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-08 00:44:26 -04:00
Mike Frysinger
164d04f4fc Blackfin: BF537: unify duplicated headers
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-08 00:44:26 -04:00
Mike Frysinger
b0c5f1cb72 Blackfin: BF52x: unify duplicated headers
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-08 00:44:26 -04:00
Mike Frysinger
0807fe0a49 Blackfin: drop duplicate system mmr and L1 scratch defines
Common code already takes care of setting up these defines when a port
hasn't specified them, so punt the duplicate values.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-08 00:44:26 -04:00
Mike Frysinger
cca07417d5 Blackfin: BF50x: new processor port
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-08 00:44:26 -04:00
Mike Frysinger
5a9a2c55d1 Blackfin: fix bd_t handling
The recent global data changes (making the size autogenerated) broke the
board info handling on Blackfin ports as we were lying and lumping the
bd_t size in with the gd_t size.  So use the new dedicated bd_t size to
setup its own address in memory.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-08 00:44:26 -04:00
Mike Frysinger
704f1f0c20 Blackfin: bf537: fix L1 data defines
The __BFIN_DEF_ADSP_BF537_proc__ define isn't setup anymore, so use
the one coming from the compiler.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-08 00:44:26 -04:00
Mike Frysinger
baaa4f9ce2 Blackfin: serial: clean up muxing a bit
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-08 00:44:26 -04:00
Mike Frysinger
fbcf8e8c75 Blackfin: move CONFIG_BFIN_CPU back to board config.h
This is a revert of 821ad16fa9 as Wolfgang doesn't like the new code.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-08 00:44:26 -04:00
Mike Frysinger
ec4c6933ff Blackfin: unify bootmode based LDR_FLAGS setup
Unify this convention for all Blackfin boards.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-08 00:44:26 -04:00
Mike Frysinger
fbb21ff047 Blackfin: drop CONFIG_SYS_TEXT_BASE from boards
We don't want/use this value for Blackfin boards, so punt it and have the
common code error out when people try to use it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-08 00:44:26 -04:00
Mike Frysinger
7d69dfd2a8 Blackfin: skip RAM display for 0 mem systems
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-08 00:44:26 -04:00
Zhao Chenhui
4aa8405c91 powerpc/85xx: Add some defines & registers in immap_85xx.h
* Added SDHCDCR register to GUR struct
* Added SDHCDCR_CD_INV define related to SDHCDCR
* Added Pin Muxing define related to TDM on P102x

Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-05 10:18:39 -05:00
Haiying Wang
a52d2f816d powerpc/85xx: Add P1021 specific QE and UEC support
P1021 has some QE pins which need to be set in pmuxcr register before
using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and
UCC5 in Eth mode.  QE9 and QE12 are set for MII management. QE12 needs to
be released after MII access because QE12 pin is muxed with LBCTL signal.

Also added relevant QE support defines unique to P1021.

The P1021 QE is shared on P1012, P1016, and P1025.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-05 10:18:39 -05:00
Zhao Chenhui
c1fc2d4fc2 powerpc/85xx: don't init SDRAM when CONFIG_SYS_RAMBOOT
Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Acked-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-05 10:18:39 -05:00
Wolfgang Denk
4db2fa7f94 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Conflicts:
	drivers/usb/host/ehci-pci.c

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-04-05 12:24:20 +02:00
Kumar Gala
c2a63f48fb powerpc/8xxx: Fix typo for address hashing message
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:43 -05:00
Kyle Moffett
c7fd27ccfb mpc8xxx: DDR2/DDR3: Clean up DIMM-type switch statements
The numeric constants in the switch statements are replaced by #defines
added to the common ddr_spd.h header.  This dramatically improves the
readability of the switch statments.

In addition, a few of the longer lines were cleaned up, and the DDR2
type for an SO-RDIMM module was added to the DDR2 switch statement.

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kim Phillips <kim.phillips@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:43 -05:00
Kyle Moffett
e820a131f4 fsl_ddr: Don't use full 64-bit divides on 32-bit PowerPC
The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit
integer divide operations to convert between nanoseconds and DDR clock
cycles given arbitrary DDR clock frequencies.

Since all of the inputs to this are 32-bit (nanoseconds, clock cycles,
and DDR frequencies), we can easily restructure the computation to use
the "do_div()" function to perform 64-bit/32-bit divide operations.

On 64-bit this change is basically a no-op, because do_div is
implemented as a literal 64-bit divide operation and the instruction
scheduling works out almost the same.

On 32-bit PowerPC a fully accurate 64/64 divide (__udivdi3 in libgcc) is
over 1.1kB of code and thousands of heavily dependent cycles to compute,
all of which is linked from libgcc.  Another 1.2kB of code comes in for
the function __umoddi3.

It should be noted that nothing else in U-Boot or the Linux kernel seems
to require a full 64-bit divide on my 32-bit PowerPC.

Build-and-boot-tested on the HWW-1U-1A board using DDR2 SPD detection.

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Acked-by: York Sun <yorksun@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:43 -05:00
Laurentiu TUDOR
33e683541e powerpc/85xx: Fix setting of LIODN prop in PCIe nodes on P3041/P5020
We utilize the compatible string to find the node to add fsl,liodn
property to.  However P3041 & P5020 don't have "fsl,p4080-pcie"
compatible for their PCIe controllers as they aren't backwards compatible.

Allow the macro's to specify the PCIe compatible to use to allow SoC
uniqueness.  On P3041 & P5020 we utilize "fsl,qoriq-pcie-v2.2" for the
PCIe controllers.

Signed-off-by: Laurentiu TUDOR <Laurentiu.Tudor@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:43 -05:00
bhaskar upadhaya
f5feb5afb2 powerpc/85xx: Update timer-frequency prop in ptp_timer node of device tree
Fix up the device tree property associated with the IEEE 1588 timer
source frequency.  Currently we only support the IEEE 1588 timer source
being the internal eTSEC system clock (for those SoCs with IEEE 1588
support).  The eTSEC clock is ccb_clk/2.

Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:43 -05:00
Kumar Gala
939cdcdc62 powerpc/85xx: Fix determining Fman freq on P1023
On the P1023 the Fman freq is equivalent to the system bus freq, not 1/2
of it.  Also we only have one Fman so no need for the code to deal with
a second.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:43 -05:00
Kumar Gala
b5c8753fa1 powerpc/85xx: Fixup determining PME, FMan freq
On CoreNet based SoCs (P2040, P3041, P4080, P5020) we have some
additional rules to determining the various frequencies that PME & FMan
IP blocks run at.

We need to take into account:
* Reduced number of Core Complex PLL clusters
* HWA_ASYNC_DIV (allows for /2 or /4 options)

On P2040/P3041/P5020 we only have 2 Core Complex PLLs and in such SoCs
the PME & FMan blocks utilize the second Core Complex PLL.  On SoCs
like p4080 with 4 Core Complex PLLs we utilize the third Core Complex
PLL for PME & FMan blocks.

On P2040/P3041/P5020 we have the added feature that we can divide the
PLL down further by either /2 or /4 based on HWA_ASYNC_DIV.  On P4080
this options doesn't exist, however HWA_ASYNC_DIV field in RCW should be
set to 0 and this gets a backward compatiable /2 behavior.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:43 -05:00
Kumar Gala
c657d898bc powerpc/85xx: Specify CONFIG_SYS_FM_MURAM_SIZE
CONFIG_SYS_FM_MURAM_SIZE varies from SoC to SoC to specify it in
config_mpc85xx.h for those parts with a Frame Manager.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:42 -05:00
Priyanka Jain
7d640e9bdf powerpc/85xx: Corrected sdhc clock value for P1010
SDHC clock is equal to CCB on P1010 and P1014 not CCB/2.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:42 -05:00