Commit Graph

4 Commits

Author SHA1 Message Date
Thierry Reding 95bdf6469d e2220-1170: Remove hard-coded counter frequency
The counter frequency is derived from clk_m on Tegra, but that clock can
be configured by the primary bootloader to run at the same frequency as
the oscillator (38.4 MHz on Tegra210) or a divided down frequency (most
typically 19.2 MHz). Remove the hard-coded frequency and allow the timer
setup code to query the correct value at runtime.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-09-16 16:10:23 -07:00
Stephen Warren b9f269f60f ARM: tegra: replace V_PROMPT define with kconfig
Commit 181bd9dc61 "kconfig: add config option for shell prompt" replaced
define V_PROMPT with Kconfig option SYS_PROMPT. This crossed with patches
adding Tegra T210 boards. Migrate the boards to the new scheme.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-09-16 16:10:22 -07:00
Stephen Warren bfac084723 ARM: tegra: fix COUNTER_FREQUENCY for T210
While T210 boards all have 38.4MHz crystals, per the TRM, the only
supported configuration is to divide the crystal frequency by 2 to
generate clk_m, which is what feeds the ARM generic timers amongst other
things. Fix the value of COUNTER_FREQUENCY to reflect this divide-by-2.

When I queried the 19.2 value in Tom's original T210 patches, I wasn't
aware of this extra divide-by-2, and didn't notice any effect from the
incorrect value, since its only used if U-Boot is booted in EL3, whereas
I'm booting it in EL2.

Reported-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-09-16 16:10:22 -07:00
Stephen Warren b6920095c5 ARM: tegra: Add e2220-1170 board
E2220-1170 is a Tegra210 bringup board with onboard SoC, DRAM,
eMMC, SD card slot, HDMI, USB micro-B port, and sockets for various
expansion modules.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-08-06 10:50:03 -07:00