Commit graph

9 commits

Author SHA1 Message Date
Jean-Christophe PLAGNIOL-VILLARD
6d0f6bcf33 rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-18 21:54:03 +02:00
John Rigby
8a490422be ADS5121: Fix NOR and CPLD ALE timing for rev 2 silicon
MPC5121 rev 2 silicon has a new register for controlling how long
CS is asserted after deassertion of ALE in multiplexed mode.

The default is to assert CS together with ALE.  The alternative
is to assert CS (ALEN+1)*LPC_CLK clocks after deassertion of ALE.

The default is wrong for the NOR flash and CPLD on the ADS5121.

This patch turns on the alternative for CS0 (NOR) and CS2 (CPLD)
it does so conditionally based on silicon rev 2.0 or greater.

Signed-off-by: Martha J Marx <mmarx@silicontkx.com>
Signed-off-by: John Rigby <jrigby@freescale.com>
2008-08-28 13:36:43 -06:00
Kenneth Johansson
6689484ccd mpc5121: Move iopin features from board specific to common files.
And in the process eliminate some duplicate register defines.

Signed-off-by: Kenneth Johansson <kenneth@southpole.se>
2008-08-05 20:45:34 -06:00
John Rigby
5f91db7f58 MPC5121e ADS PCI support take 3
Adds PCI support for MPC5121

Tested with drivers/net/rtl8139.c

Support is conditional since PCI on old silicon does not work.

ads5121_PCI_config turns on PCI

In this version, condition compilation of PCI code has been moved
from ifdef in board/ads5121/pci.c to board/ads5121/Makefile as
suggested by Jean-Christophe PLAGNIOL-VILLARD

Signed-off-by: John Rigby <jrigby@freescale.com>
2008-03-02 21:44:59 +01:00
John Rigby
de55d18df3 Change IPS freq to 66MHz
Recommended frequency is 66MHz
Change divider from 4 to 3.

Signed-off-by: John Rigby <jrigby@freescale.com>
2008-02-07 01:08:05 +01:00
Grzegorz Bernacki
334e442e6f Set ips dividor to 1/4 of csb clock.
Previous setting cause ips clock to be out of spec. This bug was found by John
Rigby from Freescale.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
2008-01-17 09:31:58 +01:00
John Rigby
51b67d06fa ADS5121: MAX slew rate for PATA pins
Signed-off-by: John Rigby <jrigby@freescale.com>
2008-01-13 23:36:22 +01:00
Wolfgang Denk
b1b54e3520 Coding style cleanup, update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
2007-08-02 21:27:46 +02:00
Rafal Jaworowski
8993e54b6f [ADS5121] Support for the ADS5121 board
The following MPC5121e subsystems are supported:

- low-level CPU init
- NOR Boot Flash (common CFI driver)
- DDR SDRAM
- FEC
- I2C
- Watchdog

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
Signed-off-by: Jan Wrobel <wrr@semihalf.com>
2007-07-27 14:43:59 +02:00