Commit graph

13 commits

Author SHA1 Message Date
Michal Simek
7a78bd2679 fpga: Define bitstream type based on command selection
Clean up partial, full and compressed bitstream handling.
U-Boot supports full bitstream loading and partial
based on detection which is not 100% correct.
Extending fpga_load/fpga_loadbitstream() with one more
argument which stores bitstream type.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-20 15:23:46 +02:00
Michal Simek
14cfc4f373 fpga: xilinx: Simplify load/dump/info function handling
Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13 09:13:59 +02:00
Michal Simek
f8c1be9816 fpga: xilinx: Avoid CamelCase for in Xilinx_desc
No functional changes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13 09:12:53 +02:00
Michal Simek
2a6e3869f2 fpga: spartan3: Avoid CamelCase
No functional changes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-13 09:12:52 +02:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
York Sun
472d546054 Consolidate bool type
'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.

All other #define, typedef and enum are removed. They are all consistent with
true = 1, false = 0.

Replace FALSE, False with false. Replace TRUE, True with true.
Skip *.py, *.php, lib/* files.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-04-01 16:33:52 -04:00
Stefano Babic
33e1e01820 fpga: Spartan-3: let print the progress if configured
CONFIG_SYS_FPGA_PROG_FEEDBACK was already introduced to print
the current status of FPGA loading - an undef in the code made this
CONFIG_ useless.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-01-05 16:20:12 +01:00
Wolfgang Denk
e6a857da74 fpga: constify to fix build warning
Fix compiler warning:

cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data'
from incompatible pointer type

Adding the needed 'const' here entails a whole bunch of additonal
changes all over the FPGA code.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Andre Schwarz <andre.schwarz@matrix-vision.de>
Cc: Murray Jensen <Murray.Jensen@csiro.au>
Acked-by: Andre Schwarz<andre.schwarz@matrix-vision.de>
2011-08-01 15:19:40 +02:00
Wolfgang Wegner
b0bc8b70ff add Xilinx_abort_fn to Xilinx_Spartan3_Slave_Serial_fns
Currently the hardware was left in an undefined state in case Spartan3
serial load failed. This patch adds Xilinx_abort_fn to give the board
a possibility to clean up in this case.

Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de>
2010-11-30 21:59:21 +01:00
Wolfgang Wegner
89083346d0 add block write function to spartan3 slave serial load
Using seperate function calls for each bit-bang of slave serial
load can be painfully slow. This patch adds the possibility to
supply a block write function that loads the complete block of
data in one call (like it can already be done with Altera FPGAs).
On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load
time from around 15 seconds to around 3 seconds

Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
2010-03-24 11:08:43 -05:00
Peter Tyser
6385b28116 fpga: Remove relocation fixups
PPC boards are the only users of the current FPGA code which is littered
with manual relocation fixups.  Now that proper relocation is supported
for PPC boards, remove FPGA manual relocation.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-10-03 10:17:56 +02:00
Matthias Fuchs
670cbde8da fpga: Fix Spartan III FPGA booting
This patch does some minor fixing of the Xilinx Spartan III
FPGA boot code:

- Fixed call order of post configuration callback and
  success message printing (result of copy-paste?)
- remove obsolete comment
- minor coding style cleanup

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
2009-02-21 22:52:44 +01:00
Jean-Christophe PLAGNIOL-VILLARD
c8aa7dfc18 FPGA: move fpga drivers to drivers/fpga
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-12-05 22:41:33 +01:00
Renamed from common/spartan3.c (Browse further)