Commit graph

6 commits

Author SHA1 Message Date
Bin Meng
3ff2f001c2 x86: Enable CONFIG_PCI_CONFIG_HOST_BRIDGE for all boards
It looks that x86 chipset always contains a host bridge at pci
b.d.f 0.0.0, so enable this for all boards.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-26 07:54:08 -07:00
Simon Glass
a77fda1f7d net: Move CONFIG_E1000 options to Kconfig
Move config for the E1000 Ethernet driver to Kconfig and tidy up affected
boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-08-21 16:40:23 -05:00
Bin Meng
44a8b96f64 x86: baytrail: Add all IDE/SATA PCI device IDs
The BayTrail SoC has 4 different PCI devices IDs regarding to IDE
and AHCI. Add these IDs in pci_ids.h and also add the other SATA
ID in the Bayley Bay and MinnowMax board configuration header.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-14 03:24:20 -06:00
Simon Glass
dcfe4a54ed x86: Move CONFIG_X86_SERIAL to Kconfig
Move this config option to Kconfig and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:42 -06:00
Bin Meng
fe3fbd3024 x86: bayleybay: Configure PCI IRQ
Add PCI IRQ routing information in the board device tree and enable
writing PIRQ routing table and MP table.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-05 08:42:39 -06:00
Bin Meng
9b911bed78 x86: Add Intel Bayley Bay board support
Intel Bayley Bay board is a BayTrail based board. Add this board
with existing baytrail fsp support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-05 08:42:39 -06:00