Commit graph

3 commits

Author SHA1 Message Date
Gabe Black
9a7da182fa x86: Fill in the dram info using the e820 map on coreboot/x86
This way when that dram "banks" are displayed, there's some useful information
there. The number of "banks" we claim to have needs to be adjusted so that it
covers the number of RAM e820 regions we expect to have/care about.

This needs to be done after "RAM" initialization even though we always run
from RAM. The bd pointer in the global data structure doesn't automatically
point to anything, and it isn't set up until "RAM" is available since, I
assume, it would take too much space in the very constrained pre-RAM
environment.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:39 -08:00
Gabe Black
f08fa7a201 x86: Add infrastructure to extract an e820 table from the coreboot tables
Also approximate the size of RAM using the largest RAM address available
in the tables. There may be areas which are marked as reserved which are
actually at the end of RAM.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-12-19 13:26:16 +11:00
Gabe Black
ef5a5b0049 x86: Initial commit for running as a coreboot payload
Add a target for running u-boot as a coreboot payload in boards.cfg, a
board, CPU and a config. This is a skeleton implementation which always
reports the size of memory as 64 MB.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
2011-12-19 13:26:15 +11:00