Commit graph

29991 commits

Author SHA1 Message Date
Tim Harvey
75f21e3131 imx: ventana: Add support for GW551x
The GW551x is a small form factor board based on the IMX6 SoC that includes:
 * up to 512MB DDR3 memory
 * up to 2GB NAND flash
 * 1x miniPCIe socket (with USB)
 * HDMI out (micro-HDMI)
 * HDMI in (micro-HDMI)
 * TTL level I/O (supported by GW16111 breakout board):
  * I2C
  * 2x UART
  * CAN
  * 2x DIO (GPIO/PWM)
  * USB OTG

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-04-22 14:39:09 +02:00
Tim Harvey
0c81b14fac imx: ventana: disable IMX6 watchdogs on GW51xx RevA and RevB
A board level errata causes the IMX6 watchdog to be unstable on the GW51xx
RevA and RevB boards which can cause the watchdog to trip extremely early
(under 5seconds) under certain operating conditions. Disable the watchdog
node in the device-tree to work around this issue.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-04-22 14:39:09 +02:00
Tim Harvey
1274bd2c27 imx: ventana: fix various sparse warnings
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-04-22 14:39:08 +02:00
Tim Harvey
30dc880ad1 imx: ventana: config: enable EXT4 filesystem read/write support
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-04-22 14:39:08 +02:00
Tim Harvey
f6747cda78 imx: ventana: config: enable edid support
Enable the 'i2c edid' command to query and display data from an attached
HDMI monitor of LVDS display with an EDID device.

Example:
 Ventana > i2c dev 2 && i2c edid 0x50

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-04-22 14:39:08 +02:00
Tim Harvey
8cc25eb877 imx: ventana: config: Support ramdisk
Set the initrd_high env so that ramdisk range can be properly set.

See commit 7e9603e and README

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-04-22 14:39:08 +02:00
Tim Harvey
9543e9542e imx: ventana: config: add USB Mass Storage (ums) support
Add support for the USB mass storage gadget to enable access to on-board
storage.

Example:
 Ventana > ums 0 mmc 0 # provide ums access to the uSD
 Ventana > ums 0 usb 0 # provide ums access to the first USB device
 Ventana > ums 0 sata 0 # provide ums access to an mSATA device

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-04-22 14:39:08 +02:00
Tim Harvey
4717e1395e imx: ventana: set LTC3676 PMIC to appropriate values per datasheet
The IMX6 Datasheets specifies that when the IMX6 LDO is enabled
(internal Anatop LDO's for VDD_ARM, VDD_SOC, and VDD_xPU) you need to
provide 1350mV on VDD_ARM_IN and VDD_SOC_IN for IMX6Q@1GHz (Automotive)
and 1275mV for IMX6DL@800MHz (Industrial). While we are still about 50mV
shy on the IMX6Q operating at 1GHz we set it to the max we can and leave it
up to the kernel to implement a regulator driver for the LTC3676 and put
the LDO's in bypass mode which allows us to drop the voltages by 125mV
respectively.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-04-22 14:39:07 +02:00
Tim Harvey
b0b83347a9 imx: ventana: add support for 4Gb density mem devices with IMX6DL
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-04-22 14:39:07 +02:00
Tim Harvey
29f0d6b1d0 imx: ventana: enable precharge power-down fast-exit mode
Enable fast-exit precharge mode necessary for some DDR3 devices being
used on Ventana boards.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-04-22 14:39:07 +02:00
Tim Harvey
a51de276d8 imx: ventana: add usb_pcisel hwconfig support
The GW52xx has a MUX that can direct front-panel USB OTG to one of the
miniPCIe sockets (for use with a cellular modem for example). Use hwconfig
to steer this.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-04-22 14:39:07 +02:00
Tim Harvey
3ee26ecc72 imx: ventana: remove unused GPIO configuration
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-04-22 14:39:07 +02:00
Tim Harvey
e806b22984 imx: ventana: assign default ethprime dynamically
Gateworks Ventana boards don't all use IMX6 FEC, so lets define default
ethprime based off the first detected device.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-04-22 14:39:06 +02:00
Tim Harvey
0a6ee033d7 imx: ventana: add i210 support
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-04-22 14:39:06 +02:00
Tim Harvey
306568d35a imx: ventana: disable 4k tftp/nfs packets
I've encountered issues when using 4k packets through certain switches. For
now disable this and go back to using MTU size packets.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-04-22 14:39:06 +02:00
Fabio Estevam
b8ce6fe261 mx6: Add initial SPL support for HummingBoard-i2eX
Add the initial SPL support for HummingBoard-i2eX, which is based on a
MX6 Dual.

For more information about HummingBoard, please check:
http://www.solid-run.com/products/hummingboard/

Based on the work from Jon Nettleton and Rabeeh Khoury.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-04-22 14:39:06 +02:00
Tim Harvey
08daa258e6 fdt: add new fdt_fixup_display function to configure display
Add 'fdt_fixup_display' function to fixup device-tree native-mode property
of display-timings node to select timings for a specific display.
This is useful if a device-tree has configurations for multiple
display timings for undetectable displays.

see kernel Documentation/devicetree/bindings/video/display-timing.txt

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-22 14:39:06 +02:00
Tim Harvey
78c5a18087 arm: mx6: ddr: add pd_fast_exit flag to system information
DDR3 has a special Precharge power-down mode: fast-exit vs slow-exit.

In slow-exit mode the DLL is off but in some quiescent state that makes it easy
to turn on again in tXPDLL cycles (about 10tCK) vs the full tDLLK (512tCK).
In fast-exist mode the DLL is maintained such that it is ready again in about
3tCK.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-04-22 14:35:35 +02:00
Jörg Krause
32f9ef3e2b ARM: mxs: Get boot mode from OCRAM
Reading the boot mode pins after power-up does not necessarily represent the
boot mode used by the ROM loader. For example the state of a pin may have
changed because a recovery switch which was pressed to enter USB mode is
already released after plugging in USB.

The ROM loader stores the value a fixed address in OCRAM. Use this value
instead of reading the boot map pins.

The GLOBAL_BOOT_MODE_ADDR for i.MX28 is taken from an U-Boot patch for the
MX28EVK:
http://repository.timesys.com/buildsources/u/u-boot/u-boot-2009.08/u-boot-2009.08-mx28-201012211513.patch

Leave the boot mode detection for the i.MX23 untouched. Someone has to test
whether the i.MX ROM loader does also store the boot mode in OCRAM and if the
address match.

This patch superseeds my incorrect patch:
ARM: mxs: get boot mode from OTP
http://patchwork.ozlabs.org/patch/454930/

Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
Cc: Stefano Babic <sbabic@denx.de>
2015-04-22 14:24:09 +02:00
Peng Fan
4fbad92e73 mtd: spi: check return value of spi_setup_slave
Need to check value of spi_setup_slave and spi_setup_slave_fdt.
If their return value 'bus' is NULL, there is no need to pass it
to following spi_flash_probe_tail.

If 'bus' is null, the original function flow is as following:
spi_flash_probe
	|->spi_setup_slave
	|->spi_probe_bus_tail
		|->spi_flash_probe_slave
		|->spi_free_slave
Alougth check the pointer in spi_free_slave is ok, checking the return value
of spi_setup_slave and spi_setup_slave_fdt is better.

Before this fix:
"
=> sf probe 0:2
FSL_QSPI: Not a valid cs !
SF: Failed to set up slave
data abort
pc : [<fff66dcc>]          lr : [<fff7628c>]
reloc pc : [<87814dcc>]    lr : [<8782428c>]
sp : fdf4fcf0  ip : e630396c     fp : fe0d0888
r10: fffa2538  r9 : fdf4feb8     r8 : 02625a00
r7 : 00000002  r6 : fff94ec0     r5 : 00000000  r4 : 9355553c
r3 : 1af0593c  r2 : cb3fe030     r1 : fff94eb8  r0 : e59ff018
Flags: nZCv  IRQs off  FIQs off  Mode SVC_32
Resetting CPU ...
"

After this fix:
"
=> sf probe 0:2
FSL_QSPI: Not a valid cs !
Failed to initialize SPI flash at 0:2
"
No data abort using this patch.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-04-22 17:06:13 +05:30
Stefan Roese
ed62756dcf cmd_sf: Fix problem with "sf update" and unaligned length
On SoCFPGA, using "sf update" with an non-4byte aligned length leads
to a hangup (and reboot via watchdog). This is because of the unaligned
access in the cadence QSPI driver which is hard to prevent since the
data is written into a 4-byte wide FIFO. This patch fixes this problem
by changing the behavior of the last sector write (not sector aligned).

The new code is even simpler and copies the source data into the temp
buffer and now uses the temp buffer to write the complete sector. So
only one SPI sector write is used now instead of 2 in the old version.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Gerlando Falauto <gerlando.falauto@keymile.com>
Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Cc: Holger Brunck <holger.brunck@keymile.com>
Acked-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-04-22 16:49:51 +05:30
Pavel Machek
d15e74f16c spi flash: fix trivial problems
Fix typos and too big #ifdef.

Signed-off-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-04-22 16:49:51 +05:30
Siva Durga Prasad Paladugu
8c48a68346 zynq: spi: Remove unnecessary error condition
Removed the unnecessary error check from spi_xfer
as the bitlen zero is possible now to deassert the
chip select for which no data is required to be transfered.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-04-22 16:49:51 +05:30
Siva Durga Prasad Paladugu
06bc1756c5 sf: Poll both the read status and flag status
Poll both the Read status and Flag status registers
for sucessful erase and program operations for the
Micron devices with E_FSR flag set in params table.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-04-22 16:49:51 +05:30
Siva Durga Prasad Paladugu
d2f763162a sf: Correct the macros as per new array fast read command
Correct the macros as per insertion of array fast read
command CMD_READ_ARRAY_FAST in spi_read_cmds_array in file
sf_probe.c

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-04-22 16:49:51 +05:30
Prabhakar Kushwaha
a2a55e518f driver/fsl-mc: Add support of MC Flibs
Freescale's Layerscape Management Complex (MC) provide support various
objects like DPRC, DPNI, DPBP and DPIO.
Where:
	DPRC: Place holdes for other MC objectes like DPNI, DPBP, DPIO
	DPBP: Management of buffer pool
	DPIO: Used for used to QBMan portal
	DPNI: Represents standard network interface

These objects are used for DPAA ethernet drivers.

Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com>
Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:27:35 -07:00
Bhupesh Sharma
b7f57ac0d8 fsl-ch3/README: Add description for NOR flash layout (firmware images)
This patch adds description for NOR flash layout (firmware images)
in the README file for LS2085A platforms.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:27:07 -07:00
Bhupesh Sharma
422cb08acb armv8/fsl-lsch3: Add Freescale Debug Server driver
The Debug Server driver is responsible for loading the Debug
server FW on the Service Processor (Cortex-A5 core) on LS2085A like
SoCs and then polling for the successful initialization of the same.
TOP MEM HIDE is adjusted to ensure the space required by Debug Server
FW is accounted for. MC uses the DDR area which is calculated as:

MC DDR region start = Top of DDR - area reserved by Debug Server FW

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:26:29 -07:00
Zhao Qiang
1fb5ff9ae7 QE/DeepSleep: add QE deepsleep support for arm
Muram will power off during deepsleep, and the microcode of qe
in muram will be lost, it should be reload when resume.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:19:20 -07:00
Zhao Qiang
ae42eb035e QE/DeepSleep: add QE deepsleep support for mpc85xx
Muram will power off during deepsleep, and the microcode of qe
in muram will be lost, it should be reload when resume.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:19:19 -07:00
Nikhil Badola
b4e78faab3 drivers:usb: Check if USB Erratum A005697 is applicable on BSC913x
Check if USB Erratum A005697 is applicable on BSC913x and
add corresponding  property in the device tree via device
tree fixup which is used by linux driver

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:19:19 -07:00
Minghuan Lian
0070459048 pci/layerscape: fix link and class issues to support ls2085a
1. LS2085a provides PCIE_LUT_DBG register rather than PCIE_LDBG
   to show the link status, so the patch fixes it.
2. Increase the delay time to make sure that link training
   has finished.
3. Return invalid value when accessing multi-function device
4. For LS2085a DBI_RO_WR_EN bit is cleared as default, so we
   must set this bit before change DBI register value.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:19:19 -07:00
Minghuan Lian
d42bd3453a pci/layerscape: remove unnecessary pcie_layerscape.h
The patch uses the common function name ft_pci_setup to replace
ft_pcie_setup, then removes unnecessary pcie_layerscape.h because
all the functions have been declared in common.h.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:19:19 -07:00
Nikhil Badola
4a4323af3d drivers:usb:fsl: Add affected SOCs for USB Erratum A007792
Add following affected SOCs and their personalities for USB
Erratum A007792 :
        T1040 Rev 1.1
        T1024 Rev 1.0

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:19:19 -07:00
Nikhil Badola
0c77106095 drivers:usb: Add device-tree fixup to identify socs having dual phy
Identify soc(s) having dual phy so as to add "utmi_dual" as phy_mode
for all these socs. This is required for supporting deel-sleep feature
in linux for usb driver

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:19:19 -07:00
gaurav rana
98cb0efde8 Add bootscript support to esbc_validate.
1. Default environment will be used for secure boot flow
 which can't be edited or saved.
2. Command for secure boot is predefined in the default
 environment which will run on autoboot (and autoboot is
 the only option allowed in case of secure boot) and it
 looks like this:
 #define CONFIG_SECBOOT \
 "setenv bs_hdraddr 0xe8e00000;"                 \
 "esbc_validate $bs_hdraddr;"                    \
 "source $img_addr;"                             \
 "esbc_halt;"
 #endif
3. Boot Script can contain esbc_validate commands and bootm command.
 Uboot source command used in default secure boot command will
 run the bootscript.
4. Command esbc_halt added to ensure either bootm executes
 after validation of images or core should just spin.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:19:19 -07:00
Alison Wang
997c67d98b ls102xa: ddr4: Use LPUART as console output to verify DCU driver
On QDS board with DDR4 DIMM, LPUART is used as console
output to verify DCU driver. This patch adds
ls1021aqds_ddr4_nor_lpuart_defconfig for this support.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:19:19 -07:00
Yao Yuan
09227dd9df ls1021atwr: add hwconfig setting to do pin mux
Freescale LS1021ATWR share some pins. Hwconfig option is used to
allows users to choose the pin functions.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
[York Sun: revised commit message]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:19:19 -07:00
Alison Wang
036f3f3379 arm/ls102xa:Add support of conditional workaround implementation as per SoC ver
For LS102xA, some workarounds are only used in VER1.0, so silicon
version detection are added for QDS and TWR boards.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:19:19 -07:00
Linus Walleij
d77447fdb1 serial: pl01x: fix PL010 regression
commit aed2fbef5e
"dm: serial: Tidy up the pl01x driver"
caused a regression on (real hardware) PL010 by omitting
to update the line control register when switching baudrate.

Fix this by inlining the missing write to the baud control
register.

Also renaming the set_line_control() function to
pl011_set_line_control() since this function is clearly
PL011-specific, and it won't suffice to call that to
set up line control.

Tested on the Integrator/AP hardware.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-21 10:05:42 -04:00
Andrey Skvortsov
a436d61279 kconfig: remove duplicated CMD_DNS option
two CMD_DNS options were added by commit 60296a835c ("commands: add more
command entries in Kconfig")

Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-04-21 10:03:54 -04:00
Marek Vasut
b284d268af arm: socfpga: spl: Add stub sdram.h
Since the SoCFPGA SDRAM support is not yet applied to u-boot, we still
need to be able to compile the codebase. Introduce stub functions which
temporarily supplement the missing SDRAM setup functions.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
2015-04-21 12:37:12 +02:00
Marek Vasut
96bfdf01ca spi: Add Cadence QSPI controller Kconfig entry
Add Cadence QSPI controller Kconfig entry.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
2015-04-21 12:23:38 +02:00
Marek Vasut
67d7a9d643 spi: Add Designware SPI controller Kconfig entry
Add DWC SPI controller Kconfig entry.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
2015-04-21 12:23:36 +02:00
Dinh Nguyen
8b73dda86b arm: socfpga: spl: update peripheral pll for dev kit
"commit 0d13a0051b2c arm: socfpga: Sync Cyclone V DK PLL configuration"
mistakenly changed CONFIG_HPS_MAINPLLGRP_VCO_NUMER to 39, the correct
value should be 79.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-21 12:23:17 +02:00
Dinh Nguyen
0ef44d1150 arm: socfpga: spl: add board_init_f to SPL
Remap SDRAM to 0x0, and clear OCRAM's ECC in board_init_f().

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2015-04-21 12:23:17 +02:00
Dinh Nguyen
a74732b611 arm: socfpga: spl: Add s_init stub
Add a stub s_init function in the board file. The reason why the stub function
is needed is that most of the work is now being done in board_init_f(), there
is no need for the SPL to do anything s_init(). However, since lowlevel_init()
is still branching to s_init(), we need stub function for now, until
lowlevel_init() morphs into s_init().

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-21 12:23:17 +02:00
Dinh Nguyen
3c38de5464 arm: socfpga: fix uart0 pin mux configuration
commit "07d30b6c3129 arm: socfpga: Sync Cyclone V DK pinmux configuration"
incorrectly set the muxing for UART0 on the Cyclone V DK.

This fixes it up so UART0 is working again.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-21 12:23:17 +02:00
Dinh Nguyen
9ad3a4ace2 arm: socfpga: spl: Add SDRAM check
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-21 12:23:17 +02:00
Dinh Nguyen
18ad2de4b2 arm: socfpga: spl: Adjust the SYS_INIT_RAM_SIZE to have room for the spl malloc
We need to adjust the SYS_INIT_RAM_SIZE to have room for the
SPL_MALLOC_SIZE.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-21 12:23:17 +02:00