Commit graph

14 commits

Author SHA1 Message Date
Peng Fan
3cb4f25cc7 video: ipu: avoid overflow issue
Multiplication, as "clk->parent->rate * 16" may overflow. So use
do_div to avoid such issue.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Signed-off-by: Sandor Yu <sandor.yu@nxp.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
2016-03-14 22:47:41 +01:00
Heiko Schocher
cb9f8e6a73 video, ipu: make ldb clock frequency overwritable through board code
the ldb clock can be setup in board code (for example set through PLL5).
Update the ldb_clock rate also through board code.

This should be removed, if a clock framework is availiable.

Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
2015-04-20 09:36:59 +02:00
Heiko Schocher
0ced25beb5 video, ipu: make ldb_clock configurable
make the ldb_clock configurable through the new define
CONFIG_SYS_LDB_CLOCK. This is needed as the ldb clock is not
always 650000000, for example on the aristainetos2 board,
where the ldb clock derives from PLL5 clock.

Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
2015-04-20 09:34:45 +02:00
Jeroen Hofstee
c5fe2532ac video: ipu: prevent warnings with W=1
- make local functions static
- remove unused is_interlaced function

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-10-25 07:27:37 -04:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Liu Ying
945d069fb5 ipu common: reset ipuv3 correctly
This patch checks self-clear sw_ipu_rst bit in
SCR register of SRC controller to be cleared
after setting it to high to reset IPUv3. This
makes sure that IPUv3 finishes sofware reset.
A timeout mechanism is added to stop polling
on the bit status in case the bit could not be
cleared by the hardware automatically within
10 millisecond.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
2012-11-06 22:24:11 +01:00
Benoît Thébaudeau
1f5e4ee0b9 mx5: Use explicit clock gate names
Use clock gate definitions having names showing clearly the gated clock instead
of names giving only a register field index.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
2012-10-15 11:54:10 -07:00
Eric Nelson
0bb7e316f0 i.MX6: provide functional names for CCM_CCGR0-CCGR6 bit fields
Add meaningful constants for each clock channels and use them for
enabling and disabling i.MX6 clocks.

Includes an update to enable/disable the IPU1 clock in
drivers/video/ipu_common to remove IMX5x register access
when used on i.MX6 as discussed in V1:

     http://patchwork.ozlabs.org/patch/185129/

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2012-10-15 11:54:08 -07:00
Eric Nelson
cf65d478ab ipu_common: Add ldb_clk for use in parenting the pixel clock
Add ldb_clk for use in parenting the pixel clock.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-10 11:35:39 +02:00
Fabio Estevam
9fbdb1aac5 ipu_common: Do not hardcode the ipu_clk frequency
Do not hardcode the ipu_clk frequency and let the board file pass this value.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-10 11:35:39 +02:00
Fabio Estevam
477bca22f6 ipu_common: Rename MXC_CCM_BASE
Rename MXC_CCM_BASE to CCM_BASE_ADDR as this is already defined for MX6.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-10 11:35:39 +02:00
Fabio Estevam
e4942ad703 ipu_common: Let clk_ipu_enable/disable only run on MX51 and MX53
The registers accessed inside clk_ipu_enable/disable are not present on MX6,
so make sure they only run on MX51 and MX53.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-10 11:35:39 +02:00
Fabio Estevam
913db79427 ipu_common: Only apply the erratum to MX51
The following erratum :

"ENGcm08316
IPU: Clarification regarding the bypass mode registers setup for
display and camera interfaces"

only applies to mx51, so restrict its usage for this SoC only.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-07-10 11:35:38 +02:00
Stefano Babic
575001e40c MX51: Add IPU driver for video support
The patch is a porting of the IPU Linux driver
developed by Freescale to have framebuffer
functionalities in u-boot. The port is based on
kernel 2.6.31 commit cc4fe714041805997b601fe8e5dd585d8a99297f,
as delivered by Freescale [i.MX BSP].
Most features are dropped from the original driver and
only LCD support is the goal of this porting.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2010-10-22 00:05:05 +02:00