Commit graph

10 commits

Author SHA1 Message Date
Rob Herring
cdb23792e8 config: remove platform CONFIG_SYS_HZ definition part 1/2
Remove platform CONFIG_SYS_HZ definition for configs A-Z*.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-11-04 11:05:59 -05:00
Tom Rini
c2120fbfbc Merge branch 'master' of git://git.denx.de/u-boot-i2c
The sandburst-specific i2c drivers have been deleted, conflict was just
over the SPDX conversion.

Conflicts:
	board/sandburst/common/ppc440gx_i2c.c
	board/sandburst/common/ppc440gx_i2c.h

Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:50:24 -04:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Heiko Schocher
00f792e0df i2c, fsl_i2c: switch to new multibus/multiadapter support
- added to fsl_i2c driver new multibus/multiadpater support
- adapted all config files, which uses this driver

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
2013-07-23 08:34:53 +02:00
Gabor Juhos
842033e696 pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option
The pci_indirect.c file is always compiled when
CONFIG_PCI is defined although the indirect PCI
bridge support is not needed by every board.

Introduce a new CONFIG_PCI_INDIRECT_BRIDGE
config option and only compile indirect PCI
bridge support if this options is enabled.

Also add the new option into the configuration
files of the boards which needs that.

Compile tested for powerpc, x86, arm and nds32.
MAKEALL results:

powerpc:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 641
  Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB )
  ----------------------------------------------------------
  Note: the warnings for ELPPC and MPC8323ERDB are present even
  without the actual patch.

x86:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 1
  ----------------------------------------------------------

arm:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 311
  ----------------------------------------------------------

nds32:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 3
  ----------------------------------------------------------

Cc: Tom Rini <trini@ti.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
2013-06-07 14:17:01 -04:00
Tom Rini
219f4788d3 hush.c: Move default CONFIG_SYS_PROMPT_HUSH_PS2 to hush.c
Exactly one board has defined CONFIG_SYS_PROMPT_HUSH_PS2 to a value
different than "> " which is vision2.  I have Cc'd the maintainer here
as I strongly suspect this is a bug rather than intentional behavior.

Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-06-20 20:36:51 +02:00
Marek Vasut
ae291b7315 HWW1U1A: Fix CMD_SHA1 -> CMD_SHA1SUM
Fix typo

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Kyle.D.Moffett@boeing.com
Acked-by: Anatolij Gustschin <agust@denx.de>
2012-04-19 22:01:13 +02:00
Kyle Moffett
0ecb55132b eXMeritus HWW-1U-1A: Add support for the AT24C128N I2C EEPROM
This EEPROM is hardware-write-protected and used to persist key
information such as the serial number and MAC addresses even if the
primary environment sector in NOR FLASH is overwritten.

During manufacturing, the environment is initialized from Linux and then
the key parameters copied to the EEPROM via U-Boot:

  env export -c -s 0x2000 $loadaddr serial# macaddr mac1addr mac2addr
  eeprom write $loadaddr 0x0000 0x2000

The chip is then locked via hardware for delivery.

When doing a field U-Boot upgrade, the environment is erased and reset
to the defaults to avoid problems with "hwconfig" changes, etc.  After
loading the new U-Boot image, the hardware data is reloaded:

  i2c dev 0
  eeprom read $loadaddr 0x0000 0x2000
  env import -c $loadaddr 0x2000
  saveenv

The first three commands are saved in the "restore_eeprom" variable for
user convenience.  (EG: "run restore_eeprom && saveenv")

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-01-11 13:57:53 -06:00
Kyle Moffett
7985f7e3ff eXMeritus HWW-1U-1A: Minor environment variable tweaks
Most of the ethernet connections are internal links with specialized
hardware and are not useful for "dhcp" or general-purpose networking;
U-Boot should not be cycling through them.  Force the primary external
network interface in "ethprime" and disable the interface cycling with
"ethrotate=no".

Additionally, the environment variable "preboot" has its own config
option and means something entirely different from what the HWW-1U-1A
variable was intended for.  Rename the board variable to "setbootargs"
to avoid potential confusion.

Finally, fix an incorrect address for the kernel in FLASH memory.

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-01-11 13:57:51 -06:00
Kyle Moffett
f8bbb4dad0 mpc85xx: Add board support for the eXMeritus HWW-1U-1A devices
The eXMeritus HWW-1U-1A unit is a DO-160-certified 13lb 1U chassis
with 3 independent TEMPEST zones.  Two independent P2020 computers may
be found inside each zone.  Complete hardware support is included.

High-level hardware overview:
  * DO-160 certified for passenger aircraft (noncritical)
  * TEMPEST ceritified for RED/BLACK separation
  * 3 zones per chassis, 2 computers per zone (total of 6)
  * Dual-core 1.066GHz P2020 per computer
  * One 2GB DDR2 SO-RDIMM module per computer (upgradable to 4GB)
  * Removable 80GB or 160GB Intel X18-M SSD per computer
  * Front-accessible dual-port E1000E per computer
  * Front-accessible serial console per computer
  * Front-accessible USB port per computer
  * Internal Gigabit crossover within each TEMPEST zone
  * Internal unidirectional fiber links across TEMPEST zones
  * Battery-backed DS1339 I2C RTC on each CPU.

Combined, each 13lb 1U chassis contains 12GB RAM, 12 cores @ 1.066GHz,
12 front-accessible Gigabit Ethernet ports and 960GB of solid-state
storage with a total power consumption of ~200W.

Additional notes:
  * SPD detection is only known to work with the DO-160-certified DIMMs

  * CPU reset is a little quirky due to hardware misfeature.  Proper
    support for the hardware reset mechanism has been left for a later
    patch series to address.

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-12-09 08:40:12 -06:00