Commit graph

51 commits

Author SHA1 Message Date
Marek Vasut
5368c55d4c COMMON: Use __stringify() instead of MK_STR()
Kill multiple occurances and redeclaration of MK_STR
in favor of __stringify().

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
2012-10-15 11:53:47 -07:00
Tom Rini
219f4788d3 hush.c: Move default CONFIG_SYS_PROMPT_HUSH_PS2 to hush.c
Exactly one board has defined CONFIG_SYS_PROMPT_HUSH_PS2 to a value
different than "> " which is vision2.  I have Cc'd the maintainer here
as I strongly suspect this is a bug rather than intentional behavior.

Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-06-20 20:36:51 +02:00
Paul Gortmaker
3e3262bd14 sbc8548: enable support for hardware SPD errata workaround
Existing boards by default have an issue where the LBC SDRAM
SPD EEPROM and the DDR2 SDRAM SPD EEPROM both land at 0x51.

After the hardware modification listed in the README is made,
then the DDR2 SPD EEPROM appears at 0x53.  So this implements
a board specific get_spd() by taking advantage of the existing
weak linkage, that 1st tries reading at 0x53 and then if that
fails, it falls back to the old 0x51.

Since the old dependency issue of "SPD implies no LBC SDRAM"
gets removed with the hardware errata fix, remove that restriction
in the code, so both LBC SDRAM and SPD can be selected.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-01-11 13:59:14 -06:00
Paul Gortmaker
2a6b3b74d8 sbc8548: relocate fixed ddr init code to ddr.c file
Nothing to see here, just a relocation of the fixed ddr init
sequence to live in the actual ddr.c file itself.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-01-11 13:59:12 -06:00
Paul Gortmaker
7e44f2b710 sbc8548: Make enabling SPD RAM configuration work
Previously, SPD configuration of RAM was non functional on
this board.  Now that the root cause is known (an i2c address
conflict), there is a simple end-user workaround - remove the
old slower local bus 128MB module and then SPD detection on the
main DDR2 memory module works fine.

We make the enablement of the LBC SDRAM support conditional on
being not SPD enabled.  We can revisit this dependency as the
hardware workaround becomes available.

Turning off LBC SDRAM support revealed a couple implict dependencies
in the tlb/law code that always expected an LBC SDRAM address.

This has been tested with the default 256MB module, a 512MB
a 1GB and a 2GB, of varying speeds, and the SPD autoconfiguration
worked fine in all cases.

The default configuration remains to go with the hard coded
DDR config, so the default build will continue to work on boards
where people don't bother to read the docs.  But the advantage
of going to the SPD config is that even the small default module
gets configured for CL3 instead of CL4.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-01-11 13:59:07 -06:00
Paul Gortmaker
5f4c6f0db9 sbc8548: Fix LBC SDRAM initialization settings
These were cloned from the mpc8548cds platform which has
a different memory layout (1/2 the size).  Set the values
by comparing to the register file for the board used during
JTAG init sequence:

	LSDMR1		0x2863B727	/* PCHALL */
	LSDMR2		0x0863B727	/* NORMAL */
	LSDMR3		0x1863B727	/* MRW    */
	LSDMR4		0x4063B727	/* RFEN   */

This differs from what was there already in that the RFEN is
not bundled in all four steps implicitly, but issued once
as the final step.

The other difference seen when comparing vs. the register file init,
is that since the memory is split across /CS3 and /CS4, the dummy
writes need to go to 0xf000_0000 _and_ to 0xf400_0000.

We also rewrite the final LBC SDRAM inits as macros, as there is
no real need for them to be a local variable that is modified
on the fly at runtime.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-01-11 13:59:03 -06:00
Paul Gortmaker
f0aec4ea33 sbc8548: enable ability to boot from alternate flash
This board has an 8MB soldered on flash, and a 64MB SODIMM
flash module.  Normally the board boots from the 8MB flash,
but the hardware can be configured for booting from the 64MB
flash as well by swapping CS0 and CS6.  This can be handy
for recovery purposes, or for supporting u-boot and VxBoot
at the same time.

To support this in u-boot, we need to have different BR0/OR0
and BR6/OR6 settings in place for when the board is configured
in this way, and a different TEXT_BASE needs to be used due
to the larger sector size of the 64MB flash module.

We introduce the suffix _8M and _64M for the BR0/BR6 and the
OR0/OR6 values so it is clear which is being used to map what
specific device.

The larger sector size (512k) of the alternate flash needs
a larger malloc pool, otherwise you'll get failures when
running saveenv, so bump it up accordingly.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-01-11 13:58:14 -06:00
Paul Gortmaker
3fd673cf36 sbc8548: relocate 64MB user flash to sane boundary
The current situation has the 64MB user flash at an awkward
alignment; shifted back from 0xfc00_0000 by 8M, to leave an 8MB hole
for the soldered on boot flash @ EOM.  But to switch to optionally
supporting booting off the 64MB flash, the 64MB will then be mapped
at the sane address of 0xfc00_0000.

This leads to awkward things when programming the 64MB flash prior
to transitioning to it -- i.e. even though the chip spans from
0xfb80_0000 to 0xff7f_ffff, you would have to program a u-boot image
into the two sectors from 0xfbf0_0000 --> 0xfbff_ffff so that it was
in the right place when JP12/SW2.8 were switched to make the 64MB on
/CS0. (i.e. the chip is only looking at the bits in mask 0x3ff_ffff)

We also have to have three TLB entries responsible for dealing with
mapping the 64MB flash due to this 8MB of misalignment.

In the end, there is address space from 0xec00_0000 to 0xefff_ffff
where we can map it, and then the transition from booting from one
config to the other will be a simple 0xec --> 0xfc mapping.  Plus we
can toss out a TLB entry.

Note that TLB0 is kept at 64MB and not shrunk down to the 8MB boot
flash; this means we won't have to change it when the alternate
config uses the full 64MB for booting, in TLB0.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-01-11 13:58:10 -06:00
Paul Gortmaker
af35be6ac9 Revert "SBC8548: fix address mask to allow 64M flash"
This reverts commit ccf1ad535a.

The commit "SBC8548: fix address mask to allow 64M flash"
essentially made this change:

  * OR6:
- *    Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
+ *    Addr Mask = 64M = OR6[0:16] = 1111 1000 0000 0000 0

But this makes no sense, as section 13.3.1.2.1 in the
MPC8548ERM v2 clearly indicates the masks:

	1111_1111_1000_0000_0	8 Mbytes
	1111_1100_0000_0000_0	64 Mbytes
	1111_1000_0000_0000_0	128 Mbytes

So the original value was correct, and the commit was invalid,
causing a 128MB mapping for a 64MB flash device.  The problem
rears its head when trying to configure u-boot to have access
to both flash, since the default memory map is:

	FB80_0000 – FF7F_FFFF 32-bits 64MB FLASH SODIMM
	FF80_0000 – FFFF_FFFF 8-bits 8MB FLASH

By extending the mapping of the 64MB flash to 128MB, it now
conflicts with the normal 8MB boot flash, causing issues.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-01-11 13:58:07 -06:00
Joe Hershberger
b3f44c21ea common: cosmetic: CONFIG_BOOTFILE checkpatch compliance
Remove MK_STR from places that consume CONFIG_BOOTFILE to force all definitions to be string literals.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2011-10-22 01:21:35 +02:00
Joe Hershberger
8b3637c662 common: cosmetic: CONFIG_ROOTPATH checkpatch compliance
Remove MK_STR from places that consume CONFIG_ROOTPATH to force all definitions to be string literals.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2011-10-22 01:21:15 +02:00
Mike Frysinger
31a4f1e5b6 board configs: drop NET_MULTI references
Now that none of the core checks CONFIG_NET_MULTI, there's not much point
in boards defining it.  So scrub all references to it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-10-05 22:22:16 +02:00
Timur Tabi
e46fedfeb2 powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros
Introduce the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW
macros, which contain the high and low portions of CONFIG_SYS_CCSRBAR_PHYS.
This is necessary for the assembly-language code that relocates CCSR, since
the assembler does not understand 64-bit constants.

CONFIG_SYS_CCSRBAR_PHYS is automatically defined from the
CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, so it
should not be defined in a board header file.  Similarly,
CONFIG_SYS_CCSRBAR_DEFAULT is defined for each SOC in config_mpc85xx.h, so
it should also not be defined in the board header file.

CONFIG_SYS_CCSR_DO_NOT_RELOCATE is a "short-cut" macro that guarantees that
CONFIG_SYS_CCSRBAR_PHYS is set to the same value as CONFIG_SYS_CCSRBAR_DEFAULT,
and so CCSR will not be relocated.

Since CONFIG_SYS_CCSRBAR_DEFAULT is locked to a fixed value, multi-stage U-Boot
builds (e.g. NAND) are required to relocate CCSR only during the last stage
(i.e. the "real" U-Boot).  All other stages should define
CONFIG_SYS_CCSR_DO_NOT_RELOCATE to ensure that CCSR is not relocated.

README is updated with descriptions of all the CONFIG_SYS_CCSRBAR_xxx macros.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:04 -05:00
Wolfgang Denk
25ddd1fb0a Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value
CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not
being able to use "sizeof(struct global_data)" in assembler files.
Recent experience has shown that manual synchronization is not
reliable enough.  This patch renames CONFIG_SYS_GBL_DATA_SIZE into
GENERATED_GBL_DATA_SIZE which gets automatically generated by the
asm-offsets tool.  In the result, all definitions of this value can be
deleted from the board config files.  We have to make sure that all
files that reference such data include the new <asm-offsets.h> file.

No other changes have been done yet, but it is obvious that similar
changes / simplifications can be done for other, related macro
definitions as well.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
2010-10-26 21:05:30 +02:00
Wolfgang Denk
553f09823c Rename CONFIG_SYS_INIT_RAM_END into CONFIG_SYS_INIT_RAM_SIZE
CONFIG_SYS_INIT_RAM_END was a misnomer as it suggests this might be
some end address; to make the meaning more clear we rename it into
CONFIG_SYS_INIT_RAM_SIZE

No other code changes are performed in this patch, only minor editing
of white space (due to the changed length) and the comments was done,
where noticed.

Note that the code for the PATI and cmi_mpc5xx board configurations
looks seriously broken.  Last known maintainers on Cc:

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Denis Peter <d.peter@mpl.ch>
Cc: Martin Winistoerfer <martinwinistoerfer@gmx.ch>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
2010-10-26 21:03:25 +02:00
Peter Tyser
d98b0523cf powerpc: Cleanup BOOTFLAG_* references
Now that warm booting is not supported, there isn't a need for the
BOOTFLAG_COLD and BOOTFLAG_WARM defines, so remove them.

Note that this change makes the board info bd_bootflags field useless.
It will always be set to 0, but we leave it around so that we don't
break the board info structure that some OSes are expecting to be passed
from U-Boot.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-10-18 22:38:56 +02:00
Wolfgang Denk
2ae1824196 Makefile: move all Power Architecture boards into boards.cfg
Clean up Makefile, and drop a lot of the config.mk files on the way.

We now also automatically pick all boards that are listed in
boards.cfg (and with all configurations), so we can drop the redundant
entries from MAKEALL to avoid building these twice.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-10-18 22:12:04 +02:00
Wolfgang Denk
14d0a02a16 Rename TEXT_BASE into CONFIG_SYS_TEXT_BASE
The change is currently needed to be able to remove the board
configuration scripting from the top level Makefile and replace it by
a simple, table driven script.

Moving this configuration setting into the "CONFIG_*" name space is
also desirable because it is needed if we ever should move forward to
a Kconfig driven configuration system.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-10-18 22:07:10 +02:00
Wolfgang Denk
d24f2d321d mkconfig: change CONFIG_MK_ prefix into plain CONFIG_
When planning for more generalization and Makefile cleanup it became
obvious that the introduction of a separate CONFIG_MK_ name space for
config options that were set through scripting in the Makefile was
not a good idea.

Originally the idea was to provide a script-free approach to supply
configuration options - there was no real need for a separate name
space. But when we now convert the existing Makefile entries to make
use of this approach, it would mean that we have to touch a large
number of board config files and add #ifdef / #define sequences to
"convert" from the CONFIG_MK_ to the CONFIG_ name space.

It seems much cleaner to get rid of this somewhat arbitrary _MK
string now for the few boards that actually use it.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2010-10-18 22:01:21 +02:00
Stefan Roese
24956642ef Remove unused CONFIG_SERIAL_SOFTWARE_FIFO feature
This patch removes the completely unused CONFIG_SERIAL_SOFTWARE_FIFO
feature from U-Boot. It has only been implemented for PPC4xx and was not
used at all. So let's remove it and make the code smaller and cleaner.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
2010-09-23 09:02:05 +02:00
Kim Phillips
5be58f5fc8 powerpc/85xx: configure autocompletion support
because it's convenient.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-08-01 11:18:44 -05:00
Kumar Gala
99d9c07edc powerpc/85xx: Move PCI/PCIe address defines into common immap_85xx.h
Remove dupliacted setting of PCI/PCIe address and offsets in board
config.h.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-20 04:37:11 -05:00
Becky Bruce
199e262eb3 mpc85xx: Add reginfo command
The new command dumps the TLBCAM, the LAWs, and the BR/OR regs.
Add CONFIG_CMD_REGINFO to the config for all MPC85xx parts.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-16 10:55:09 -05:00
Paul Gortmaker
dd9ca98f26 sbc8548: reclaim wasted sector in boot flash
By nature of being based off the MPC8548CDS board, this
board inherited an ENV_SIZE setting of 256k.  But since
it has a smaller flash device (8MB soldered on), it has
a native sector size of 128k, and hence the ENV_SIZE was
causing 2 sectors to be used for the environment.

By removing the unused sector, we can push TEXT_BASE up
closer to the end of address space and reclaim that
sector for any other application.  This also fixes the
mismatch between TEXT_BASE and MONITOR_LEN reported by
Kumar earlier.

Since this board also supports the ability to boot off
the 64MB SODIMM flash, this change is forward looking
with that in mind; i.e. the settings for MONITOR_LEN
and ENV_SIZE will work when the 512k sectors of the
SODIMM flash are used for alternate boot in the future.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-30 08:29:47 -05:00
Paul Gortmaker
2738bc8df6 sbc8548: allow enabling PCI via a make config option
Prior to this commit, to enable PCI, you had to go manually
edit the board config header, and if you had 33MHz PCI, you
had to manually change CONFIG_SYS_NS16550_CLK too, which was
not real user friendly,

This adds the typical PCI and clock speed make targets to the
toplevel Makefile in accordance with what is being done with
other boards (i.e. using the "-t" to mkconfig).

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:00 -05:00
Paul Gortmaker
fdc7eb90b5 sbc8548: update PCI/PCI-e support code
The PCI/PCI-e support for the sbc8548 was based on an earlier
version of what the MPC8548CDS board was using, and in its
current state it won't even compile.  This re-syncs it to match
the latest codebase and makes use of the new shared PCI functions
to reduce board duplication.

It borrows from the MPC8568MDS, in that it pulls the PCI-e I/O
back to 0xe280_0000 (where PCI2 would be on MPC8548CDS), and
similarly it coalesces the PCI and PCI-e mem into one single TLB.

Both PCI-x and PCI-e have been tested with intel e1000 cards
under linux (with an accompanying dts change in place)

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:00 -05:00
Paul Gortmaker
11d5a629f8 sbc8548: correct local bus SDRAM size from 64M to 128M
The size of the LB SDRAM on this board is 128MB, spanning CS3
and CS4.  It was previously only being configured for 64MB on
CS3, since that was what the original codebase of the MPC8548CDS
had.  In addition to setting up BR4/OR4, this also adds the TLB
entry for the second half of the SDRAM.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:00 -05:00
Paul Gortmaker
9b3ba24f18 sbc8548: enable access to second bank of flash
The sbc8548 has a 64MB SODIMM flash module off of CS6 that
previously wasn't enumerated by u-boot.  There were already
BR6/OR6 settings for it [used by cpu_init_f()] but there
was no TLB entry and it wasn't in the list of flash banks
reported to u-boot.

The location of the 64MB flash is "pulled back" 8MB from
a 64MB boundary, in order to allow address space for the
8MB boot flash that is at the end of 32 bit address space.
This means creating two 4MB TLB entries for the 8MB chunk,
and then expanding the original boot flash entry to 64MB
in order to cover the 8MB boot flash and the remainder
(56MB) of the user flash.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:00 -05:00
Paul Gortmaker
7b1f1399e8 sbc8548: delete unused MPC8548CDS info carried over from port
There are a couple defines and PCI bridge quirks related to the PCI
backplane of the MPC8548CDS that have no meaning in the context of
the port to the sbc8548 board, so delete them.

Also, the form factor of the sbc8548 is a standalone board with a
single PCI-X and a single PCI-e slot.  That pretty much guarantees
that it will never be a PCI agent itself, so the host/agent and root
complex/end node distinctions have been removed.

Similarly, since there is no physical connector mapping to PCI2, so
all references of PCI2 in the board support files have been removed
as well.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:04:59 -05:00
Peter Tyser
bafdf9aa9d 85xx: Remove unused CONFIG_CLEAR_LAW0 defines
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:37 -05:00
Kumar Gala
b0fe93eda6 85xx: Use common LSDMR defines from asm/fsl_lbc.h
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-03-30 13:33:49 -05:00
Paul Gortmaker
58da8890d5 sbc8548: use proper PHY address
The values given for the PHY address were wrong, so the code
read no valid PHY ID, and fell through to the generic PHY
support, which would work on 1000M but would not auto negotiate
down to 100M or 10M.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2008-12-19 18:32:48 -06:00
Paul Gortmaker
ad22f9273c sbc8548: enable command line editing by default.
Lets make things a bit more user friendly.  It isn't 1985 anymore.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2008-12-19 18:32:47 -06:00
Paul Gortmaker
bd93105fa1 sbc8548: don't enable the 3rd and 4th eTSEC
These interfaces don't have usable connectors on the board, so don't
bother enumerating or configuring them.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2008-12-19 18:32:47 -06:00
Peter Tyser
ba490b7761 Remove unused CONFIG_ADDR_STREAMING defines
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2008-12-14 12:42:42 +01:00
Jon Loeliger
801a194616 Removed unused CONFIG_L1_INIT_RAM symbol.
Prevent further viral propogation of the unused
symbol CONFIG_L1_INIT_RAM by just removing it.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
2008-12-01 10:28:50 -06:00
Kumar Gala
2dba0dea98 85xx: Convert all fsl_pci_init users to new APIs
Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS,
MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows()
and ft_fsl_pci_setup().

With these changes the board code is a bit smaller and we get dma-ranges
set in the device tree for these boards.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-24 17:35:12 -05:00
Jean-Christophe PLAGNIOL-VILLARD
6d0f6bcf33 rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-18 21:54:03 +02:00
Jean-Christophe PLAGNIOL-VILLARD
0e8d158664 rename CFG_ENV macros to CONFIG_ENV
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-09-10 22:48:06 +02:00
Jean-Christophe PLAGNIOL-VILLARD
5a1aceb068 rename CFG_ENV_IS_IN_FLASH in CONFIG_ENV_IS_IN_FLASH
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-09-10 22:48:04 +02:00
Kumar Gala
33b9079ba2 FSL DDR: Convert sbc8548 to new DDR code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-08-27 11:43:51 -05:00
Jean-Christophe PLAGNIOL-VILLARD
00b1883a4c drivers/mtd: Move conditional compilation to Makefile
rename CFG_FLASH_CFI_DRIVER to CONFIG_FLASH_CFI_DRIVER

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-08-13 01:40:42 +02:00
Wolfgang Denk
53677ef18e Big white-space cleanup.
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).

Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-05-21 00:14:08 +02:00
Jeremy McNicoll
ccf1ad535a SBC8548: fix address mask to allow 64M flash
Fix incorrect mask to enable all 64MB of onboard flash.
Previously U-Boot incorrectly mapped only 8MB of flash, this
patch correctly maps all the available flash.

Signed-off-by: Jeremy McNicoll <jeremy.mcnicoll@windriver.com>
2008-05-04 00:18:48 +02:00
Kumar Gala
f69766e4b5 85xx: Add the concept of CFG_CCSRBAR_PHYS
When we go to 36-bit physical addresses we need to keep the concept of
the physical CCSRBAR address seperate from the virtual one.

For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:03 -05:00
Jean-Christophe PLAGNIOL-VILLARD
495d162374 sbc8548: Fix cfi flash bank declaration
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-02-27 16:27:16 -06:00
Kumar Gala
7dc358bb0d 85xx: Get ride of old TLB setup code
Now that all boards have been converted, remove old config code and the
config option for the new style.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 02:19:18 -06:00
Kumar Gala
143b518d91 85xx: Convert SBC8540/SBC8560/SBC8548 to new TLB setup
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-17 02:10:42 -06:00
Kumar Gala
e2b159d007 85xx: convert SBC8540/SBC8560/SBC8548 over to use new LAW init code
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-16 23:21:55 -06:00
Andy Fleming
890dfef06c Remove cache config from ATUM8548 and sbc8548 configs
These boards weren't updated by Kumar's config patch because they
weren't in the tree, yet.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-01-09 16:34:51 -06:00