Commit graph

7984 commits

Author SHA1 Message Date
Thomas Chou
2de4823dc0 nios2: change virt_to_phys to use physaddr_mask in global data
As virt_to_phys() is used a lot in DMA transfer, change it
to use physaddr_mask in global data. This will save an "if"
statement and get a little faster.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
2015-11-06 09:14:11 +08:00
Thomas Chou
1cda48f333 nios2: remove the useless parenthesis in asm/io.h
Remove the useless parenthesis in asm/io.h as suggested
by Marek.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
2015-11-06 09:14:11 +08:00
Thomas Chou
1ce61cbbe7 nios2: fix map_physmem to do real cache mapping
Fix the map_physmem() to do real cache mapping.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
2015-11-06 09:14:11 +08:00
Tom Rini
ed02c532be Merge branch 'master' of git://git.denx.de/u-boot-video 2015-11-05 07:47:21 -05:00
Tom Rini
60b25259a5 Merge git://git.denx.de/u-boot-samsung 2015-11-05 07:46:45 -05:00
Tom Rini
28824407f3 Merge git://git.denx.de/u-boot-socfpga 2015-11-05 07:46:28 -05:00
Bin Meng
4b6d09449f video: Drop DEV_EXT_VIDEO flag
DEV_EXT_VIDEO does not have any actual meaning, hence drop it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-05 08:24:42 +01:00
Bin Meng
1caf934a05 video: Drop DEV_FLAGS_SYSTEM flag
DEV_FLAGS_SYSTEM does not have any actual meaning, hence drop it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-05 08:22:21 +01:00
Chin Liang See
a55f28624e arm: dts: socfpga: Increase the spi-max-frequency for QSPI flash
With a working QSPI calibration, the SCLK can now run up to 100MHz

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vikas Manocha <vikas.manocha@st.com>
Cc: Jagannadh Teki <jteki@openedev.com>
Cc: Pavel Machek <pavel@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-05 02:34:15 +01:00
Tom Rini
8168ee38c2 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2015-11-04 18:30:51 -05:00
Andy Fleming
87e29878ca mpc85xx: Add support for the Varisys Cyrus board
This board runs a P5020 or P5040 chip, and utilizes
an EEPROM with similar formatting to the Freescale P5020DS.

Large amounts of this code were developed by
Adrian Cox <adrian at humboldt dot co dot uk>

Signed-off-by: Andy Fleming <afleming@gmail.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-04 15:19:34 -08:00
Michal Simek
1e370ef7e7 ARM: zynq: Remove zc70x target
Remove zc70x target which was one setting for zc702 and zc706.
Currently zc702 and zc706 are separated.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2015-11-04 14:49:53 +01:00
Simon Glass
42800ffa79 arm: zynq: Move serial driver to driver model
Update this driver to use driver model and change all users.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-11-04 14:49:53 +01:00
Michal Simek
c2490bf546 ARM: zynqmp: Enable DM and OF binding
SPI requires DM and OF that's why enable DM for ZynqMP
and start to use configuration based on embedded OF.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-11-04 14:49:53 +01:00
Simon Glass
035c6b271d arm: zynq: dts: Add U-Boot device tree additions
We need to mark some device tree nodes so that they are available before
relocation. This enables driver model to find these automatically. In the
case of SPL it ensures that these nodes will be retained in SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-11-04 14:49:53 +01:00
Simon Glass
71556fbcbf dm: arm: zynq: Enable device tree control in SPL
Move to using device tree control in SPL so that we can use the same driver
code in both SPL and U-Boot proper.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-11-04 14:49:53 +01:00
Simon Glass
c54c0a4c1c arm: zynq: Support the debug UART
Add support for the debug UART to assist with early debugging. Enable it
for Zybo as an example.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-11-04 14:49:52 +01:00
Simon Glass
bd44758a41 arm: zynq: Drop unnecessary code in SPL board_init_f()
Move to the new way of starting up SPL. Clearing of BSS and calling
board_init_r() is now handled by crt0.S.

Also tidy up the header include order.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-11-04 14:49:52 +01:00
Michal Simek
44303dfa79 ARM: zynqmp: Add DTS for ep108 board
Add DTS for ep108 board.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Series-to: u-boot
2015-11-04 14:49:51 +01:00
Dinh Nguyen
c624d07f3f arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines
The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register,
not the mpumodrst. So the bank for these reset bits should be 1, not 0.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-11-03 17:32:16 +01:00
Wenyou Yang
a3b59b1523 mmc: atmel: Add atmel sdhci support
The SDHCI is introduced by sama5d2, named as Secure Digital Multimedia
Card Controller(SDMMC). It supports the embedded MultiMedia Card (e.MMC)
Specification V4.41, the SD Memory Card Specification V3.0, and the SDIO
V3.0 specification. It is compliant with the SD Host Controller Standard
V3.0 specification.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-11-03 14:21:31 +01:00
Wenyou Yang
c19000556e arm: at91: clock: Add the generated clock support
Some peripherals may need a second clock source that may be different
from the system clock. This second clock is the generated clock (GCK)
and is managed by the PMC via PMC_PCR.

For simplicity, the clock source of the GCK is fixed to PLLA_CLK.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-11-03 14:21:31 +01:00
Wenyou Yang
ce39680f7e arm: at91: Change the Chip ID registers' addresses
Provide the specific addresses for the Chip ID and Chip ID Extension
registers, instead of the offset, which make it use on other chips.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-11-03 14:21:30 +01:00
Shengzhou Liu
96d59e9d6a mpc85xx/t2081: enable parsing DDR ratio for T2081 rev1.1
T2081 rev 1.1 changes MEM_PLL_RAT in RCW which requires new parsing
for PLL ratio.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-02 08:51:50 -08:00
Zhao Qiang
d468377672 t1040d4rdb: assign muxed pins to qe-tdm when set hwconfig qe-tdm
qe-tdm is muxed with diu, if hwconfig setted as qe-tdm,
assign muxed pins to qe-tdm, then delete diu node from
device tree.

Signed-off-by: Zhao Qiang <qiang.zhao@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-02 08:48:20 -08:00
Minkyu Kang
55a70c51ac arm: exynos: clean up checkpatch issues
This patch will fix these checkpatch issues.

ERROR: Macros with complex values should be enclosed in parentheses
+#define DEFAULT_DQS_X4		(DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \
+				|| (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0)

		ERROR: space prohibited before that ',' (ctx:WxW)
+	writel(val , &drex0->concontrol);
 	           ^

ERROR: space prohibited before that ',' (ctx:WxW)
+	writel(val , &drex1->concontrol);
    	           ^

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-11-02 10:38:22 +09:00
Przemyslaw Marczak
5d0434315c Exynos4412: pinmux: disable pull for MMC pins
There are 8 pins for SD card in Exynos, but the MUX was configured
only for 7, since the one was used for card detection.
This caused the pin's pull wrong configuration.

This commit fixes this and the card detect can work properly,
after call this function.

Tested-on: Odroid U3 and Odroid X2.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-11-02 10:38:10 +09:00
Przemyslaw Marczak
08d6300a35 sandbox: add ADC driver
This commit adds implementation of Sandbox ADC device emulation.
The device provides:
- single and multi-channel conversion
- 4 channels with predefined conversion output data
- 16-bit resolution

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-11-02 10:38:00 +09:00
Przemyslaw Marczak
9090d1dd0e Odroid-XU3: dts: enable ADC, with request for pre-reloc bind
This ADC is required for Odroid's board revision detection.
The pre-reloc request is enabled, since board detection will
be done in one of early function call.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-11-02 10:38:00 +09:00
Przemyslaw Marczak
54b51e6b12 Exynos54xx: dts: add ADC node
This commit adds common ADC node, which is disabled as default.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-11-02 10:38:00 +09:00
Przemyslaw Marczak
4d577e0810 Odroid-XU3: enable s2mps11 PMIC support
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-11-02 10:38:00 +09:00
Przemyslaw Marczak
3b3ad9015e dm: adc: add Exynos54xx compatible ADC driver
This commit adds driver for Exynos54xx ADC subsystem.

The driver is implemented using driver model, amd provides
ADC uclass's methods for ADC single channel operations:
- adc_start_channel()
- adc_channel_data()
- adc_stop()

The basic parameters of ADC conversion, are:
- sample rate: 600KSPS
- output the data as average of 8 time conversion

ADC features:
- sample rate: 600KSPS
- resolution: 12-bit
- channels: 10 (analog multiplexer)

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-11-02 10:38:00 +09:00
Przemyslaw Marczak
d64c8adedc Exynos5422/5800: set cpu id to 0x5422
The proper CPU ID for those Exynos variants is 0x5422,
but before the 0x5800 was set. This commit fix this back.

Changes:
- set cpu id to 0x5422 instead of 0x5800
- remove macro proid_is_exynos5800()
- add macro proid_is_exynos5422()
- change the calls to proid_is_exynos5800() with new macro

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-11-02 10:37:59 +09:00
Przemyslaw Marczak
3b72b60099 Peach-Pi: dts: add cpu-model string
This platform is based on Exynos5800 but the cpu id is 0x5422.
This doesn't fit the common Exynos SoC name convention, so now,
the CPU name is defined by device tree string, to be printed
properly.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-11-02 10:37:59 +09:00
Przemyslaw Marczak
fdbb740d7c s5p: cpu_info: print "cpu-model" if exists in dts
The CPU name for Exynos was concatenated with cpu id,
but for new Exynos platforms, like Chromebook Peach Pi
based on Exynos5800, the name of SoC variant does not
include the real SoC cpu id (0x5422).

For such case, the CPU name should be defined in device tree.

This commit introduces new device-tree property for Exynos:
- "cpu-model" - with cpu name string
If defined, then the cpu id is not printed.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-11-02 10:37:59 +09:00
Josh Wu
478ec83489 at91: simplify spl board_init_f function
crt0.S do both memset the bss section and call board_init_r for us, so
remove them from board_init_f().

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-11-01 22:02:14 +01:00
Tom Rini
588eec2a86 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2015-10-30 12:56:58 -04:00
tang yuantian
4632ad773e arm: ls1021a: Add sata support on qds and twr board
Freescale ARM-based Layerscape LS102xA contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls1021aqds and ls1021atwr boards.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:02 -07:00
Hou Zhiqiang
831c068fcf armv8/ls1043a: Enable secondary cores
After the secondary cores enter U-Boot, use CONFIG_ARMV8_MULTIENTRY to
make secondary cores excute in spin loop.

Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:02 -07:00
Yangbo Lu
8ef0d5c438 armv8/ls1043ardb: esdhc: Add esdhc support for ls1043ardb
This patch adds esdhc support for ls1043ardb.

Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:01 -07:00
Shaohui Xie
e82973414d armv8/ls1043a: Add Fman support
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:01 -07:00
Gong Qianyu
3ad4472923 armv8/ls1043ardb: Add nand boot support
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:01 -07:00
Mingkai Hu
f3a8e2b7d4 armv8/ls1043ardb: Add LS1043ARDB board support
LS1043ARDB Specification:
-------------------------
Memory subsystem:
 * 2GByte DDR4 SDRAM (32bit bus)
 * 128 Mbyte NOR flash single-chip memory
 * 512 Mbyte NAND flash
 * 16 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card

Ethernet:
 * XFI 10G port
 * QSGMII with 4x 1G ports
 * Two RGMII ports

PCIe:
 * PCIe2 (Lanes C) to mini-PCIe slot
 * PCIe3 (Lanes D) to PCIe slot

USB 3.0: two super speed USB 3.0 type A ports

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
2015-10-29 10:34:01 -07:00
Mingkai Hu
8281c58fd4 armv8/fsl_lsch2: Add fsl_lsch2 SoC
Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
ARMv8 cores and 2rd generation of Chassis.

Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:00 -07:00
Mingkai Hu
9f3183d2d6 armv8/fsl_lsch3: Change arch to fsl-layerscape
There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:00 -07:00
Shaohui Xie
8225b2fd87 net: Move some header files to include/
The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM
and PPC, move it out of ppc to include/, and change the path in
drivers accordingly.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:00 -07:00
Mingkai Hu
435acd83b2 armv7/ls1021a: move ns_access to common file
Config Security Level Register is different between different SoCs,
so put the CSL register definition into the arch specific directory.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:33:58 -07:00
horia.geanta@freescale.com
5757e06c69 arm: ls102xa: enable snooping for CAAM transactions
Enable snooping for CAAM read & write transactions by
programming the SCFG snoop configuration register:
SCFG_SNPCNFGCR[SECRDSNP]
SCFG_SNPCNFGCR[SECWRSNP]

Signed-off-by: Horia Geantă <horia.geanta@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:33:58 -07:00
Aneesh Bansal
f4f0b7403a Data types defined for 64 bit physical address
Data types and I/O functions have been defined for
64 bit physical addresses in arm.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:33:57 -07:00
Alison Wang
0cbba8e953 ls102xa: fdt: Disable IFC in SD boot for QSPI
As QSPI/DSPI and IFC are pin multiplexed, IFC is disabled
in SD boot for QSPI. This patch will add fdt support for
this rule.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:33:56 -07:00