Fix ECC Correction bug where the byte offset location were double
flipped causing correction routine to toggle the wrong byte location
in the ECC segment. The ndfc_calculate_ecc routine change the order
of getting the ECC code.
/* The NDFC uses Smart Media (SMC) bytes order */
ecc_code[0] = p[2];
ecc_code[1] = p[1];
ecc_code[2] = p[3];
But in the Correction algorithm when calculating the byte offset
location, the s1 is used as the upper part of the address. Which
again reverse the order making the final byte offset address
location incorrect.
byteoffs = (s1 << 0) & 0x80;
.
.
byteoffs |= (s0 >> 4) & 0x08;
The order is change to read it in straight and let the correction
function to revert it to SMC order.
Signed-off-by: Feng Kan <fkan@amcc.com>
Acked-by: Victor Gallardo <vgallardo@amcc.com>
Acked-by: Prodyut Hazarika <phazarika@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Embedd chip select configuration into struct for gpmc config
instead of having it completely separated as suggested by
Wolfgang Denk on
http://lists.denx.de/pipermail/u-boot/2009-May/052247.html
Signed-off-by: Matthias Ludwig <mludwig@ultratronik.de>
Legacy NAND had been scheduled for removal. Any boards that use this
were already not building in the previous release due to an #error.
The disk on chip code in common/cmd_doc.c relies on legacy NAND,
and it has also been removed. There is newer disk on chip code
in drivers/mtd/nand; someone with access to hardware and sufficient
time and motivation can try to get that working, but for now disk
on chip is not supported.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Now that the 4xx NAND driver ndfc is moved to the common NAND driver
directory we don't need this #ifdef's anymore.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch adds a NAND driver for the Marvell Kirkwood SoC's
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Scott Wood <scottwood@freescale.com>
The bbt descriptors contains the pointer to the bbt pattern which
are statically initialized memory struct. When relocated to RAM,
these pointers will continue point to NOR flash(or L2 SRAM, or
other boot device). If the contents of NOR flash changed or L2
SRAM disabled, it'll hang the system.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
The S3C2410 NAND driver source file is included in the makefile instead of
the object file.
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Scott Wood <scottwood@freescale.com>
nand_util currently uses size_t which is arch dependent and not always a
unsigned long. Now use loff_t, as does the linux mtd layer.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
The BF537-STAMP Blackfin board had a driver for working with NAND devices
that are simply memory mapped. Since there is nothing Blackfin specific
about this, generalize the driver a bit so that everyone can leverage it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Update chipselect handling in davinci_nand.c so that it can
handle 2 GByte chips the same way Linux does: as one device,
even though it has two halves with independent chip selects.
For such chips the "nand info" command reports:
Device 0: 2x nand0, sector size 128 KiB
Switch to use the default chipselect function unless the board
really needs its own. The logic for the Sonata board moves out
of the driver into board-specific code. (Which doesn't affect
current build breakage if its NAND support is enabled...)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Remove CONFIG_SYS_DAVINCI_BROKEN_ECC option. It's not just nasty;
it's also unused by any current boards, and doesn't even match the
main U-Boot distributions from TI (which use soft ECC, or 4-bit ECC
on newer chips that support it).
DaVinci GIT kernels since 2.6.24, and mainline Linux since 2.6.30,
match non-BROKEN code paths for 1-bit HW ECC. The BROKEN code paths
do seem to partially match what MontaVista/TI kernels (4.0/2.6.10,
and 5.0/2.6.18) do ... but only for small pages. Large page support
is really broken (and it's unclear just what software it was trying
to match!), and the ECC layout was making three more bytes available
for use by filesystem (or whatever) code.
Since this option itself seems broken, remove it. Add a comment
about the MV/TI compat issue, and the most straightforward way to
address it (should someone really need to solve it).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Minor cleanup for DaVinci NAND code:
- Use I/O addresses from nand_chip; CONFIG_SYS_NAND_BASE won't
be defined when there are multiple chipselect lines in use
(as with common 2 GByte chips).
- Cleanup handling of EMIF control registers
* Only need one pointer pointing to them
* Remove incorrect and unused struct supersetting them
- Use the standard waitfunc; we don't need a custom version
- Partial legacy cleanup:
* Don't initialize every board like it's a DM6446 EVM
* #ifdef a bit more code for BROKEN_ECC
Sanity checked with small page NAND on dm355 and dm6446 EVMs;
and large page on dm355 EVM (packaged as two devices, not one).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Scott Wood <scottwood@freescale.com>
NAND module should not modify EMIF registers unrelated to CS2
that is used for NAND, i.e. do not modify EWAIT config register
or registers for other Chip Selects.
Without this patch, EMIF configurations made in board_init()
will be invalidated.
Signed-off-by: Thomas Lange <thomas@corelatus.se>
This patch adds NAND Flash Controller driver for MPC5121 revision 2.
All device features, except hardware ECC and power management, are
supported.
This NFC driver replaces the one orignally posted by John Rigby:
"[PATCH] Freescale NFC NAND driver"
It's a port of the Linux driver version posted by Piotr Ziecik a few
weeks ago. Using this driver has the following advantages (from my
point of view):
- Compatibility with the Linux NAND driver (e.g. ECC usage)
- Better code quality in general
- Resulting U-Boot image is a bit smaller (approx. 3k)
- Better to sync with newer Linux driver versions
The only disadvantage I can see, is that HW-ECC is not supported right
now. But this could be added later (e.g. port from Linux driver after
it's supported there). Using HW-ECC on the MCP5121 NFC has a general
problem because of the ECC usage in the spare area. This collides with
JFFS2 for example.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Piotr Ziecik <kosmo@semihalf.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: John Rigby <jcrigby@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>
This new define enables mtdcore.c compilation and with this we can
select the MTD device infrastructure needed for the reworked mtdparts
command.
We now have the 2 MTD infrastructure defines, CONFIG_MTD_DEVICE and
CONFIG_MTD_PARTITIONS. CONFIG_MTD_DEVICE is needed (as explained above)
for the "mtdparts" command and CONFIG_MTD_PARTITIONS is needed for UBI.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
This patch brings the U-Boot MTD infrastructure in sync with the current
Linux MTD version (2.6.30-rc3). Biggest change is the 64bit device size
support and a resync of the mtdpart.c file which has seen multiple fixes
meanwhile.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Kyungmin Park <kmpark@infradead.org>
This patch enables Smart Media (SMC) ECC byte ordering which is used
on the PPC4xx NAND FLASH controller (NDFC). Without this patch we have
incompatible ECC byte ordering to the Linux kernel NDFC driver.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
With this patch the NAND and OneNAND devices are registered in the MTD
subsystem and can then be referenced by the mtdcore code (e.g.
get_mtd_device_nm()). This is needed for the new "ubi part" command
syntax without the flash type parameter (nor|nand|onenand).
Signed-off-by: Stefan Roese <sr@denx.de>
This patch removes this compilation warning when CONFIG_MTD_PARTITIONS is
defined:
nand_base.c: In function 'nand_release':
nand_base.c:2922: warning: implicit declaration of function 'del_mtd_partitions'
Signed-off-by: Stefan Roese <sr@denx.de>
We need to make sure the data written to the nand flash controller makes
it there before we start polling its status register. Otherwise, we may
get stale data and return before the controller is actually ready.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Scott Wood <scottwood@freescale.com>
The NAND flash on the TQM8548_BE modules requires a short delay after
running the UPM pattern like the MPC8360ERDK board does. The TQM8548_BE
requires a further short delay after writing out a buffer. Normally the
R/B pin should be checked, but it's not connected on the TQM8548_BE.
The corresponding Linux FSL UPM driver uses similar delay points at the
same locations. To manage these extra delays in a more general way, I
introduced the "wait_flags" field allowing the board-specific driver to
specify various types of extra delay.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
For the NAND chips on the TQM8548 modules, a special chip-select logic is
used. It uses dedicated address lines to be set via UPM machine address
register (mar). This patch adds such support to the FSL-UPM driver.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch adds support for multi-chip NAND devices to the FSL-UPM
driver. The "dev_ready" callback of the "struct fsl_upm_nand" is now
called with the argument "chip_nr" to allow testing the proper chip
select line. The NAND support of the MPC8360ERDK is updated as well.
No other boards are currently using the FSL UPM driver.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch adds support for NAND_MAX_CHIPS to the MTD NAND layer.
Multi-chips devices are displayed as shown:
Device 0: 2x NAND 512MiB 3,3V 8-bit, sector size 128 KiB
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This driver implements the ECC algorithm described in
the CPU data sheet and uses the OOB layout chosen in
already-released development systems (shipped with a custom-made
u-boot 1.3.1).
Signed-off-by: Alessandro Rubini <rubini@unipv.it>
Acked-by: Andrea Gallo <andrea.gallo@stnwireless.com>
Without the timeout present an infinite loop can occur if the
NAND device is broken or not present.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Commit cfa460adfd removed support
for disabling the "No NAND device found!!!" warning when
CONFIG_SYS_NAND_QUIET_TEST was defined. This re-adds support
for silencing the warning.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Dear Wolfgang,
You are right, the patch was ugly.
The new one seems to be better.
Signed-off-by: Valeriy Glushkov <gvv@lstec.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and
changes the default from 8 to 1 for the legacy and the new MTD
NAND layer. This allows to remove all NAND_MAX_CHIPS definitions
in the board config files because none of the boards use multi
chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440
define
#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
but that's bogus and did not work anyhow.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Enable nand lock, unlock and status of lock feature.
Not every device and platform requires this, hence,
it is under define for CONFIG_CMD_NAND_LOCK_UNLOCK
Nand unlock and status operate on block boundary instead
of page boundary. Details in:
http://www.micron.com/products/partdetail?part=MT29C2G24MAKLAJG-6%20IT
Intial solution provided by Vikram Pandita <vikram.pandita@ti.com>
Includes preliminary suggestions from Scott Wood
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Rather than putting the function prototype for board_nand_init() in the one
place where it gets called, put it into nand.h so that every place that also
defines it gets the prototype. Otherwise, errors can go silently unnoticed
such as using the wrong return value (void rather than int) when defining
the function.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
The current code that determines which bank/chipselect is used for a
given NAND instance only worked for 32-bit addresses and assumed
a 1:1 mapping. This breaks in 36-bit physical configs.
The proper way to handle this is to use the virt_to_phys() and
BR_PHYS_ADDR() routinues to match the 34-bit lbc bus address
with the the virtual address the NAND code uses.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Scott Wood <scottwood@freescale.com>
Heiko Schocher
Matthias Kaehlcke
Feng Kan
Giulio Benetti
Dirk Behme
Matthias Ludwig
Scott Wood
Stefan Roese
Valeriy Glushkov
David Brownell
Wolfgang Denk
Prafulla Wadaskar
Mingkai Hu
kevin.morfitt@fearnside-systems.co.uk
Jean-Christophe PLAGNIOL-VILLARD
Mike Frysinger
David Brownell
Thomas Lange
Graf Yang
Wolfgang Grandegger
Alessandro Rubini
Peter Tyser
Nishanth Menon
Kumar Gala