Commit graph

6 commits

Author SHA1 Message Date
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Shaohui Xie
d54097b6c1 net/phy: fix select line for TN80xx
TN80xx has same PHY ID as TN2020, but it needs different setting to register
30.93 which used to select line, so we read register 30.32 which has
bit 15:12 to indicate PHY hardware version, for TN20xx we will get 3 or 2,
for TN80xx we will get 5 or 4.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:09 -05:00
Timur Tabi
a836626cc4 powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9)
The work-around for P4080 erratum SERDES9 says that the SERDES receiver
lanes should be reset after the XAUI starts tranmitting alignment signals.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-20 16:01:37 -05:00
Timur Tabi
2339e4972f phylib: wait for TN2020 to achieve SERDES lane alignment at startup
Before the Teranetics TN2020 PHY can be used, the SERDES lanes need to be
aligned, so wait for lane alignment before completing the startup sequence.

Note that this process can take up to three seconds.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-13 23:38:11 -05:00
Andy Fleming
ebfdacb42b phylib: Work around bug in Teranetics PHY
The Teranetics PHY does not properly report the link state
for fiber connections. The new PHY code actually checked the link,
and so the FM driver would refuse to talk over a linkless PHY.

But the link may actually be up, so now we always report it as up
for fiber connections on the tn2020.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2011-10-09 17:57:53 -05:00
Andy Fleming
9082eeac5d phylib: Add a bunch of PHY drivers from tsec
The tsec driver had a bunch of PHY drivers already written. This
converts them all into PHY Lib drivers, and serves as the first
set of PHY drivers for PHY Lib.

While doing that, cleaned up a number of magic numbers (though
not all of them, as PHY vendors like to keep their numbers as
magical as possible).  Also, noticed that almost all of the
vitesse/cicada PHYs had the same config/parse/startup functions,
so those have been collapsed into one.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Detlev Zundel <dzu@denx.de>
2011-04-20 15:09:34 -05:00