SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module,
not in IOMUXC, so correct the related registers' offset.
Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate
them from iomuxc pins.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: "Benoît Thébaudeau" <benoit.thebaudeau.dev@gmail.com>
Since the mx6ull adds the AIPS3, so enable its initialization.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Add i.MX6ULL major cpu type.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
The CPU detection macro is_mx6dq returns 0 on an i.MX6DQP, so we need to
check for it explicitly in order to correctly initialize the pads when
CONFIG_MX6QDL is defined.
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Now, include/linux/errno.h is a wrapper of <asm-generic/errno.h>.
Replace all include directives for <asm-generic/errno.h> with
<linux/errno.h>.
<asm-generic/...> is supposed to be included from <asm/...> when
arch-headers fall back into generic implementation. Generally, they
should not be directly included from .c files.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Add drivers/usb/host/xhci-rockchip.c]
Signed-off-by: Tom Rini <trini@konsulko.com>
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content. (both just wrap <asm-generic/errno.h>)
Replace all include directives for <asm/errno.h> with <linux/errno.h>.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <trini@konsulko.com>
The SPL code already knows which boot device it calls the spl_boot_mode()
on, so pass that information into the function. This allows the code of
spl_boot_mode() avoid invoking spl_boot_device() again, but it also lets
board_boot_order() correctly alter the behavior of the boot process.
The later one is important, since in certain cases, it is desired that
spl_boot_device() return value be overriden using board_boot_order().
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
[add newly introduced zynq variant]
Signed-aff-by: Andreas Bießmann <andreas@biessmann.org>
To i.MX6DQPlus, osc can be choosed as the source of gpt, so
add i.MX6DQPlus support in gpt_has_clk_source_osc.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
The i.MX6DQPlus support sata interface, we should not
return failure when CPU is i.MX6DQPlus.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Support i.MX6DQPlus, otherwise wrong hab address will be used
for i.MX6QDPlus.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Ulises Cardenas <Ulises.Cardenas@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Add i.MX6SOLO support for hab function.
The difference between i.MX6SOLO and i.MX6DL is
the number of CPU cores. Besides this, they work
the same.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Cc: "Benoît Thébaudeau" <benoit.thebaudeau.dev@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
According to the product website, the full names are i.MX 7Solo
and i.MX 7Dual, whereas the short form is i.MX7S and i.MX7D. Be
consistent and print the short form for both supported i.MX 7 SoCs.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
According PL310 TRM, Auxiliary Control Register
"
The register must be written to using a secure access, and it can be
read using either a secure or a NS access. If you write to this register
with a NS access, it results in a write response with a DECERR response,
and the register is not updated. Writing to this register with the L2
cache enabled, that is, bit[0] of L2 Control Register set to 1,
results in a SLVERR.
"
So If L2 cache is already enabled by ROM, chaning value of ACR
will cause SLVERR and uboot hang.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
The echo -ne "\xNN" does not work in certain bourne-compatible shells, like
dash. The recommended way of hex->char conversion is using printf(1), but
there is a pitfall here. The GNU printf does support "\xNN" format, but
according to the opengroup documentation, this is not part of POSIX. The
POSIX printf only defines "\NNN" where N is octal. Thus, for the sake of
compatibility, we use that.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Read the number of cores in the fuses to distinguish between
the dual and solo versions.
Tested on a mx7d sabresd and on a mx7solo warp7.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
To boot a auxiliary core in asymmetric multicore system, introduce the
new command "bootaux" to do it. Example of boot auxliary core from
0x70000000 where stores the boot head information that should be
parsed by auxiliary core, "bootaux 0x70000000".
Introduce Kconfig option IMX_BOOTAUX.
Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Introduce Resource Domain Controller support for i.MX.
Now i.MX6SX and i.MX7D supports this feature to assign masters
and peripherals to different domains.
Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Check for bmode before reading the boot device
to check if a serial downloader is started,
and returns UART if the serial downloader is set,
letting SPL to wait for an image if
CONFIG_SPL_YMODEM_SUPPORT is set.
This allows to load again a SPL based board
with imx_usb_loader together with a tool
such as kermit.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Tim Harvey <tharvey@gateworks.com>
CC: Fabio Estevam <Fabio.Estevam@freescale.com>
CC: Eric Nelson <eric.nelson@boundarydevices.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
Tested-by: Eric Nelson <eric@nelint.com>
Compile misc.c for mx7, since we need related function for
lcdif and nand.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Sanchayan Maity <maitysanchayan@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Need to call lcdif_power_down to make lcdif in initial state
before kernel boot. Similar issue for uboot reset with lcdif
enabled, system will hang after serveral times resetting. Need
to let lcdif initial state to make all go well.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Add mx7 secure boot support, add helper macro IS_HAB_ENABLED_BIT
to get the corresponding bit mask per SoC (mx7 or mx6) to identify
if securue boot feature is enabled/disabled.
On authenticate_image only check for mmu enabled on mx6 SoC to
force pu_irom_mmu_enabled so ROM code can perform mmu cache flush
mx7 SoC ROM code does not have this issue as ROM enables cache support
based on fuse settings.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Add CONFIG_ROM_UNIFIED_SECTIONS for mx6sx and mx6ul target
platforms to resolve corresponding HAB_RVT_BASE base address,
the RVT table contains pointers to the HAB API functions in
ROM code.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Rework secure boot support for imx6, move existing hab support
for imx6 into imx-common for SoC reuse.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
We can reuse common functions in lib/time.c, but not reimplement
functions in imx-common/time.c.
Only keep timer_init ,get_tbclk and implement timer_read_counter in
imx-common/time.c.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
The VF610 DDRMC driver code contains settings which are
board-specific. Move these out to boards so that new boards
can define their own without having to modify the driver.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
boot_mode_apply should be applied only with CONFIG_CMD_BMODE enabled.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Some i.MXes use __NA_ or 0 to avoid setting mux_mode, but the following patch
only take i.MX6/7 into consideration.
"c3c8a5748897b24f18618047804317167a531dd3 imx-common: fix iomux settings"
Use is_soc_type(MXC_CPU_MX7) to avoid breaking other i.MXes when
setting mux_mode.
In this patch, switch to use "asm/imx-common/sys_proto.h" to avoid
build break for "is_soc_type" for vf610 and mx25.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
When setting iomux for a pin mux, there is no need to check mux_ctrl_ofs.
Also If still checking mux_ctrl_ofs, we have no chance to set iomux
for i.MX7D IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00, because the mux_ctrl_ofs
for this register is 0.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
It is not very useful to have the message below on every boot
(especially when we are using early silicon):
U-Boot 2015.10-rc2-23945-g37cf215 (Sep 08 2015 - 14:12:14 -0300)
CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
CPU: Commercial temperature grade (0C to 95C)CPU: Thermal invalid data, fuse: 0x0
- invalid sensor device
, so turn the error message into debug level.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Add imx-common cpu support for imx7d SoC
- Update reset_cause for imx7d
- Enable watchdog driver built for imx7d
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Extend init_aips to support imx7 SoC, use is_soc_type
and is_cpu_type to resolve at run time aips3 settings
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Add system counter driver for imx7d and mx6ul
imx7 and imx6ul supports system counter timer as well as
GPT timer (arch/arm/imx-common/timer.c); The default for
imx7 is systemcounter timer.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Move common imx6 arch init setup, init.c can be extended
and reused to support imx7 SoC keeping init arch common
code.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Rework cache settings for imx6, move cache configuration
to imx-common/cache.c so it can be reused for newer SoC
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Rework imx_thermal driver to be used across i.MX
processor that support thermal sensor
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* Add imx7d support for iomux controller
* imx7d has two iomux controllers iomuxc (0x3033000) and iomuxc-lpsr
(0x302C0000) each conroller provides control and mux mode pad
registers but shares iomuxc input select register with iomuxc-lpsr
IOMUX_CONFIG_LPSR flag is used to properly set daisy chain settings
for iomuxc-lpsr pads.
* Since mx7d introduces LPSR IOMUX pins, add new base to IOMUX v3
driver for these LPSR pins.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Add MXC_CPU_MX6UL for i.MX6UL CPU type which is got at runtime from
DIGPROG register. But the value has been occupied by MXC_CPU_MX6D which
is not real id from DIGPROG register, so change i.MX6D to value 0x67 which
was not occupied.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Add cpu type for i.MX6QP/DP.
This patch also fix is_mx6dqp(), since get_cpu_rev can return MXC_CPU_MX6QP
and MXC_CPU_MX6DP, we should use:
(is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)).
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
is_soc_rev should return a bool value, so use "==", but not "-",
change (is_soc_rev(CHIP_REV_1_0) > 0) to (soc_rev() > CHIP_REV_1_0).
This patch also add space between "&" for cpu_type(rev) macro.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Peng Fan
Filip Brozovic
Masahiro Yamada
Robert P. J. Day
Marek Vasut
Stefan Agner
Peng Fan
Tom Rini
Fabio Estevam
Stefano Babic
Peng Fan
Adrian Alonso
Albert ARIBAUD \\(3ADEV\\)
Fabio Estevam
Bhuvanchandra DV