Before proper environment is setup, we extract hwconfig and put it into a
buffer with size HWCONFIG_BUFFER_SIZE. We need to enlarge the buffer to
accommodate longer string. Since this macro is used in multiple files, we
move it into arch/powerpc/include/asm/config.h.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Add one more argument to call function readline_into_buffer().
Fix print SPD format for negative values.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Only the first DIMM of first controller should fall back to raw timing
parameters if SPD is missing or corrupted.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Empty slot should be skipped when calculating CAS latency.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Faster DDR3 timing requires parameters exceeding previously defined
range. Extended parameters are fixed. Added some debug messages.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Restructure DDR interleaving option to support 3 and 4 DDR controllers
for 2-, 3- and 4-way interleaving.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Required by JEDEC 79-3E for high speed DDR3.
Also change "CSn disabled" message to debug.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
When the DDR3 speed goes higher, we need to utilize fine offset
from SPD.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
fsl_ddr_get_dimm_params() should be wrapped by
CONFIG_SYS_DDR_RAW_TIMING, otherwise, when using fixed_sdram() instead of
using SPD, it will cause compile error.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Fix:
interactive.c: In function 'fsl_ddr_interactive':
interactive.c:1357:15: warning: variable 'len' set but not used [-Wunused-but-set-variable]
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Newer JEDEC DDR3 SPD Specifications define several additional values for
the DDR3 module_type field which were undefined when this code was
written. Update the code to handle the newer module types.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fix:
ctrl_regs.c: In function 'set_ddr_sdram_cfg_2':
ctrl_regs.c:641:15: warning: variable 'rcw_en' set but not used [-Wunused-but-set-variable]
ctrl_regs.c: In function 'compute_fsl_memctl_config_regs':
ctrl_regs.c:951:31: warning: array subscript is above array bounds [-Warray-bounds]
ctrl_regs.c:752:34: warning: array subscript is above array bounds [-Warray-bounds]
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fix:
options.c: In function 'populate_memctl_options':
options.c:486:28: warning: variable 'pdodt' set but not used [-Wunused-but-set-variable]
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
ddr1_dimm_params.c: In function 'compute_ranksize':
ddr1_dimm_params.c:44: warning: format '%08x' expects type 'unsigned int', but
argument 2 has type 'long long unsigned int'
ddr2_dimm_params.c: In function 'compute_ranksize':
ddr2_dimm_params.c:43: warning: format '%08x' expects type 'unsigned int', but
argument 2 has type 'long long unsigned int'
ddr3_dimm_params.c: In function 'compute_ranksize':
ddr3_dimm_params.c:74: warning: format '%16lx' expects type 'long unsigned int',
but argument 2 has type 'long long unsigned int'
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Interactive DDR debugging provides a user interface to view and modify SPD,
DIMM parameters, board options and DDR controller registers before DDR is
initialized. With this feature, developers can fine-tune DDR for board
bringup and other debugging without frequently having to reprogram the flash.
To enable this feature, define CONFIG_FSL_DDR_INTERACTIVE in board header
file and set an environment variable to activate it. Syntax:
setenv ddr_interactive on
After reset, U-boot prompts before initializing DDR controllers
FSL DDR>
The available commands are
print print SPD and intermediate computed data
reset reboot machine
recompute reload SPD and options to default and recompute regs
edit modify spd, parameter, or option
compute recompute registers from current next_step to end
next_step shows current next_step
help this message
go program the memory controller and continue with u-boot
The first command should be "compute", which reads data from DIMM SPDs and
board options, performs the calculation then stops before setting DDR
controller. A user can use "print" and "edit" commands to view and modify
anything. "Go" picks up from current step with any modification and
compltes the calculation then enables the DDR controller to continue u-boot.
"Recompute" does it over from fresh reading.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Unified DDR driver is maintained for better performance, robustness and bug
fixes. Upgrading to use unified DDR driver for MPC83xx takes advantage of
overall improvement. It requires changes for board files to customize
platform-dependent parameters.
To utilize the unified DDR driver, a board needs to define CONFIG_FSL_DDRx
in the header file. No more boards will be accepted without such definition.
Note: the workaround for erratum DDR6 for the very old MPC834x Rev 1.0/1.1
and MPC8360 Rev 1.1/1.2 parts is not migrated to unified driver.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
DDR2 has different ODT table and values. Adding table according to Samsung
application note.
Fix additive latency calculation to avoid interger underflow.
Also converted typedef dynamic_odt_t to struct dynamic_odt.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The two slots on the same controller have different addresses.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Check second DIMM slot in case the first one is empty.
Honor DQS enable option for SDRAM mode register.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
DDR RCW varies at different speeds. It is common for all platform. Move it
out from corenet_ds.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Extend CAS write Latency (CWL) table to comply with DDR3 spec
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add this option to allow boards to override the default read-to-write
turnaround time for better performance.
Signed-off-by: York Sun <yorksun@freescale.com>
Checking width before setting DDR controller. SPD for DDR1 and DDR2 has
data width and primary sdram width. The latter one has different meaning
for DDR3.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
In case of empty SPD or checksum error, fallback to raw timing on
supported boards.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We used to have fixed parameters for soldered DDR chips. This patch
introduces CONFIG_SYS_DDR_RAW_TIMING to enable calculation based on timing
data from DDR chip datasheet, implemneted in board-specific files or header
files.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add support for 16-bit DDR bus. Also deal with system using 64- and 32-bit
DDR devices.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Only use DDR DIMM part number if SPD has valid length, to prevent from
display garbage in case SPD doesn't cover these fields.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
If the bus width is 32-bit, burst chop should be disabled and burst length
should be 8. Read from SPD or other source to determine the width.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Reword "The DIMM max tCKmin is ..." to "The DDR clock is faster than the slowest
DIMM(s) can support". Fixed interger type in printf as well.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The numeric constants in the switch statements are replaced by #defines
added to the common ddr_spd.h header. This dramatically improves the
readability of the switch statments.
In addition, a few of the longer lines were cleaned up, and the DDR2
type for an SO-RDIMM module was added to the DDR2 switch statement.
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kim Phillips <kim.phillips@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit
integer divide operations to convert between nanoseconds and DDR clock
cycles given arbitrary DDR clock frequencies.
Since all of the inputs to this are 32-bit (nanoseconds, clock cycles,
and DDR frequencies), we can easily restructure the computation to use
the "do_div()" function to perform 64-bit/32-bit divide operations.
On 64-bit this change is basically a no-op, because do_div is
implemented as a literal 64-bit divide operation and the instruction
scheduling works out almost the same.
On 32-bit PowerPC a fully accurate 64/64 divide (__udivdi3 in libgcc) is
over 1.1kB of code and thousands of heavily dependent cycles to compute,
all of which is linked from libgcc. Another 1.2kB of code comes in for
the function __umoddi3.
It should be noted that nothing else in U-Boot or the Linux kernel seems
to require a full 64-bit divide on my 32-bit PowerPC.
Build-and-boot-tested on the HWW-1U-1A board using DDR2 SPD detection.
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Acked-by: York Sun <yorksun@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Beside displaying RDIMM or UDIMM, this patch adds display of the model numbers
embedded in SPD.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards
pretty much do the same thing. The only variations are in how many
controllers or DIMMs per controller exist. To make this work we
standardize on the names of the SPD_EEPROM_ADDRESS defines based on the
use case of the board.
We allow boards to override get_spd to either do board specific fixups
to the SPD data or deal with any unique behavior of how the SPD eeproms
are wired up.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq()
and every 86xx board uses get_bus_freq(). If implement get_ddr_freq()
as a static inline to call get_bus_freq() we can remove
fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq()
directly.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
rcw_en bit is only available for DDR3 controllers. It is a reserved bit on
DDR1 and DDR2 controllers.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
To recognize DIMMs with ECC capability by testing ECC bit only. Not to be
confused by Address Parity bit.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The write recovery time of both registers should match. Since mode register
doesn't support cycles of 9,11,13,15, we should use next higher number for
both registers.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
When DDR data rate is higher than 1200MT/s or controller interleaving is
enabled, additional cycle for write-to-read turnaround is needed to satisfy
dynamic ODT timing.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
ctrl_regs.c: In function 'set_ddr_sdram_mode_2':
ctrl_regs.c:690:6: warning: unused variable 'i'
'i' is only used by DDR3 code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version
(major, minor, errata) to determine if unique mode registers are available.
If true, always use unique mode registers. Dynamic ODT is enabled if needed.
The table is documented in doc/README.fsl-ddr. This function may also need
to be extend for future other platforms if such a feature exists.
Enable address parity and RCW by default for RDIMMs.
Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for
quad-rank RDIMMs.
Use a formula to calculate rodt_on for timing_cfg_5.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add fsl_ddr:ecc=on in hwconfig. If ECC is enabled in board configuration file,
ECC can be turned on/off by this switch. If this switch is omitted, it is ON by
default.
Updated hwconfig calls to use local buffer.
Syntax is
hwconfig=fsl_ddr:ecc=on
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
There are several users of the hwconfig APIs (8xxx DDR) before we have
the environment properly setup. This causes issues because of the
numerous ways the environment might be accessed because of the
non-volatile memory it might be stored in. Additionally the access
might be so early that memory isn't even properly setup for us.
Towards resolving these issues we provide versions of all the hwconfig
APIs that can be passed in a buffer to parse and leave it to the caller
to determine how to allocate and populate the buffer.
We use the _f naming convention for these new APIs even though they are
perfectly useable after relocation and the environment being ready.
We also now warn if the non-f APIs are called before the environment is
ready to allow users to address the issues.
Finally, we convert the 8xxx DDR code to utilize the new APIs to
hopefully address the issue once and for all. We have the 8xxx DDR code
create a buffer on the stack and populate it via getenv_f().
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
This patch adds fsl_ddr_sdram_size to only calculate the ddr sdram size, in
case that the DDR SDRAM is initialized in the 2nd stage uboot and should not
be intialized again in the final stage uboot.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Move the parsing of hwconfig to determine if to use spd into common code
so we can share it across all boards instead of duplicating it
everywhere.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add spaces to cause the informational prints to line up with
the ones from init_func_ram() in board.c. Output now looks like
this:
....
DRAM: Detected 4096 MB of memory
This U-Boot only supports < 4G of DDR
You could rebuild it with CONFIG_PHYS_64BIT
DDR: 2 GiB (DDR2, 64-bit, CL=5, ECC off)
....
The prints from lbc_sdram_init() have also been modified to line
line up and changed to start with "LBC SDRAM" instead of the
confusing "SDRAM".
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun
Shaohui Xie
Kumar Gala
Ira W. Snyder
Marek Vasut
Kyle Moffett
Poonam Aggrwal
Haiying Wang
Becky Bruce