Commit graph

6 commits

Author SHA1 Message Date
Simon Glass
1f2be4cea4 x86: Drop CONFIG_DCACHE_RAM_MRC_VAR_SIZE from header file
This is provided in Kconfig so we don't need it here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:42 -06:00
Simon Glass
dcfe4a54ed x86: Move CONFIG_X86_SERIAL to Kconfig
Move this config option to Kconfig and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:42 -06:00
Simon Glass
ca4435ef28 x86: Move Chrome OS options to defconfig
Drop these from the header file and use Kconfig instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-05 08:42:42 -06:00
Bin Meng
786a08e0dd x86: Move VGA option rom macros to Kconfig
Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig
and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on
HAVE_VGA_BIOS. The new names are consistent with other x86 binary
blob options like HAVE_FSP/FSP_FILE/FSP_ADDR.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14 18:03:18 -06:00
Bin Meng
3d5bbbc471 x86: Set CONFIG_NR_DRAM_BANKS to 8 and move it to x86-common.h
Some x86 boards set CONFIG_NR_DRAM_BANKS to 1, which causes incorrect
DRAM size printed when booting from coreboot, like this:

	CPU: x86, vendor Intel, device 663h
	DRAM:  636 KiB
	Using default environment

Change it to 8 which should be enough for both coreboot and bare
cases, and move it to x86-common.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:38 -06:00
Simon Glass
cc285c565a x86: Move common Chromebook config into a separate file
Since Chromebooks mostly have similar configuration, put it in a common
file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-16 19:27:40 -06:00