Commit graph

15 commits

Author SHA1 Message Date
Bogdan Purcareata
3378727d13 pcie/layerscape: fix bug in bus number computation when setting msi-map
When multiple PCI cards are present in an ls2080a board, the second
card does not get its msi-map set up properly due to a bug in
computing the bus number.

The bus number returned by PCI_BDF() is not the actual PCI bus
number, but instead represents a global u-boot PCI bus number. A
given bus number is relative to hose->first_busno, so that has to be
subtracted from the PCI device id.

Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
Acked-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03 14:12:10 -07:00
Stuart Yoder
5e8e27b743 pci/layerscape: set LUT and msi-map for discovered PCI devices
msi-map properties are used to tell an OS how PCI requester IDs are
mapped to ARM SMMU stream IDs.

for all PCI devices discovered in a system:
  -allocate a LUT (look-up-table) entry in that PCI controller
  -allocate a stream ID for the device
  -program and enable a LUT entry (maps PCI requester id to stream ID)
  -set the msi-map property on the controller reflecting the
   LUT mapping

basic bus scanning loop/logic was taken from drivers/pci/pci.c
pci_hose_scan_bus().

Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:13 -07:00
Stuart Yoder
2d97fbb4c4 armv8: ls2080a: remove obsolete stream ID partitioning support
Remove stream ID partitioning support that has been made
obsolete by upstream device tree bindings that specify how
representing how PCI requester IDs are mapped to MSI specifiers
and SMMU stream IDs.

Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:12 -07:00
Bin Meng
7ba34ff09f pci: layerscape: Adjust the return value when ls_pcie_addr_valid() fails
When trying to access non-existent/unsupported PCI devices in
ls_pcie_read_config(), when ls_pcie_addr_valid() fails it returns
error code and fills in the result with 0xffffffff manually. But it
really should return zero to upper layer codes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-08 10:15:49 -05:00
Mingkai Hu
af523a0d56 pci/layerscape: add support for LS1043A PCIe LUT register access
The endian and base address of PEX LUT register region is different
between Chassis 2 and Chassis 3, so move the base address definition
to chassis specific header file and add pex_lut_* functions to access
LUT register.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:10 -08:00
Prabhakar Kushwaha
06b5301043 armv8: ls2085a: Add support of LS2085A SoC
Freescale's LS2085A is a another personality of LS2080A SoC with
support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Updated MAINTAINERS files
           Dropped #ifdef in cpu.h
           Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:10:47 -08:00
Prabhakar Kushwaha
449372148f armv8: LS2080A: Rename LS2085A to reflect LS2080A
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:04 -08:00
Mingkai Hu
9f3183d2d6 armv8/fsl_lsch3: Change arch to fsl-layerscape
There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29 10:34:00 -07:00
Varun Sethi
6923b069bd pci/layerscape: Setup mmu-masters property for the PCIe
Setup mmu-masters property for the PCIe controllers. This would be
used by the Linux SMMU driver, while setting up stream ID table mappings
for the PCIe devices.

Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-09-01 21:49:27 -05:00
Minghuan Lian
01cafcedbf drivers/pci/layerscape: Add EP mode support
The patch will initialize PCIe controller on EP mode
1. Setup bar:
   bar0 32bit 4K for specific configuration
   bar1 32bit 8K for MSIX
   bar2 64bit 4K for descriptor of memory
   bar4 64bit 1M for DMA memory test
2. Setup iATU:
   iATU inbound 0-3 to map bar transaction to memory address
   started at CONFIG_SYS_PCI_EP_MEMORY_BASE
   iATU outbound 0 to map 4G memory space

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-08-03 12:06:38 -07:00
Stuart Yoder
70e52d2115 armv8/fsl-lsch3: device tree fixups for PCI stream IDs
This patch adds the infrastructure to update device
tree nodes to convey SMMU stream IDs in the device
tree.  Fixups are implemented for PCI controllers
initially.

Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:37 -07:00
Minghuan Lian
0070459048 pci/layerscape: fix link and class issues to support ls2085a
1. LS2085a provides PCIE_LUT_DBG register rather than PCIE_LDBG
   to show the link status, so the patch fixes it.
2. Increase the delay time to make sure that link training
   has finished.
3. Return invalid value when accessing multi-function device
4. For LS2085a DBI_RO_WR_EN bit is cleared as default, so we
   must set this bit before change DBI register value.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:19:19 -07:00
Minghuan Lian
d42bd3453a pci/layerscape: remove unnecessary pcie_layerscape.h
The patch uses the common function name ft_pci_setup to replace
ft_pcie_setup, then removes unnecessary pcie_layerscape.h because
all the functions have been declared in common.h.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-21 10:19:19 -07:00
Minghuan Lian
e4e8cb7138 driver/pci: add Layerscape PCIe driver
The patch adds Freescale Layerscape PCIe driver and provides
up to 4 controllers support.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-02-24 13:10:50 -08:00
Minghuan Lian
da419027af arm: ls102xa: Update PCIe dts node status
The patch changes PCIe dts node status to 'disabled' if the
corresponding controller is disabled according to serdes protocol.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:35:56 -08:00