Commit graph

77 commits

Author SHA1 Message Date
John Rigby
6895d4510a Add support for KARO TX25 board
This is an i.MX25 base board with only NAND
so it uses nand_spl to boot.

Signed-off-by: John Rigby <jcrigby@gmail.com>

Tune configuration, add support for (redundant) environment in NAND.
Signed-off-by: Wolfgang Denk <wd@denx.de>

Acked-by: Wolfgang Denk <wd@denx.de>
CC: Fred Fan <fanyefeng@gmail.com>
CC: Tom <Tom.Rix@windriver.com>
2010-03-07 12:36:36 -06:00
Kim Phillips
fe389da6ae mpc83xx: fix out-of-tree mpc8315 nand build
commit 2e95004deb "mpc83xx: Add NAND boot support
for MPC8315E-RDB boards" symlinked nand_spl/board/freescale/mpc8315erdb to
mpc8313erdb in order to not duplicate code.

Since the main makefile builds nand_spl/board/$(BOARDDIR) (which makes sense),
and the board Makefile and linker script are the only two necessary files
to enable out-of-tree building, and other boards have duplicated nand makefiles
(e.g. 8536ds & 8569mds), it only seems prudent to copy these two files in the
name of the 8315 too.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Anton Vorontsov <avorontsov@ru.mvista.com>
Cc: Wolfgang Denk <wd@denx.de>
2010-03-02 11:24:40 -06:00
John Rigby
f3bb63a304 Add MX25 support to nand_spl fsl nfc driver
MX25 has a different version of the fsl_nfc
flash controller known as version 1.1.

Add support to the nand_spl fsl_nfc driver

Versioning differs from mainline mxc kernel driver
no consensus yet on if the naming here and in
Redboot or the kernel is "correct".

Signed-off-by: John Rigby <jcrigby@gmail.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
CC: Scott Wood <scottwood@freescale.com>
2010-01-27 14:22:41 -06:00
Liu Yu
674ef7bd02 Nand boot: Add nand boot support for MPC8569mds board
This patch add nand boot support for MPC8569mds board.

Signed-off-by: Liu Yu <yu.liu@freescale.com>
2010-01-27 14:22:40 -06:00
Kumar Gala
6d6e7c53d5 ppc/85xx: Fix inclusion of 83xx immap in 85xx builds
The nand_boot_fsl_elbc.c is shared between 83xx & 85xx however we should
not be including the immap_83xx.h when building 85xx.  We can just get
this all from common.h

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-11-04 21:39:07 -06:00
Kumar Gala
613ad28c3d ppc/85xx: Fix compiler warning in nand_spl/.../p1_p2_rdb/nand_boot.c
nand_boot.c: In function 'board_init_f':
nand_boot.c:44: warning: 'sys_clk' may be used uninitialized in this function

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-26 21:21:25 -05:00
Kumar Gala
e8967d96a0 ppc/85xx: Fix building NAND_SPL out of tree
We need to source files to exist in the O=<FOO> nand_spl dir when
we build out of tree.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-26 21:19:22 -05:00
Dipen Dudhat
f7780ec977 ppc/P1_P2_RDB: NAND Boot Support
NAND Boot support for P1 and P2 series RDB platforms.

This patch is derived from NAND Boot support on MPC8536DS.

Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-10-16 10:21:39 -05:00
Wolfgang Denk
1d96cfe8f5 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2009-09-30 23:39:36 +02:00
Mingkai Hu
9a1a0aedbb NAND boot: MPC8536DS support
MPC8536E can support booting from NAND flash which uses the
image u-boot-nand.bin. This image contains two parts: a 4K
NAND loader and a main U-Boot image. The former is appended
to the latter to produce u-boot-nand.bin. The 4K NAND loader
includes the corresponding nand_spl directory, along with the
code twisted by CONFIG_NAND_SPL. The main U-Boot image just
like a general U-Boot image except the parts that included by
CONFIG_SYS_RAMBOOT.

When power on, eLBC will automatically load from bank 0 the
4K NAND loader into the FCM buffer RAM where CPU can execute
the boot code directly. In the first stage, the NAND loader
copies itself to RAM or L2SRAM to free up the FCM buffer RAM,
then loads the main image from NAND flash to RAM or L2SRAM
and boot from it.

This patch implements the NAND loader to load the main image
into L2SRAM, so the main image can configure the RAM by using
SPD EEPROM. In the first stage, the NAND loader copies itself
to the second to last 4K address space, and uses the last 4K
address space as the initial RAM for stack.

Obviously, the size of L2SRAM shouldn't be less than the size
of the image used. If so, the workaround is to generate another
image that includes the code to configure the RAM by SPD and
load it to L2SRAM first, then relocate the main image to RAM
to boot up.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-30 08:42:06 -05:00
Stefan Roese
95b602bab5 ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper case
The latest PPC4xx register cleanup patch missed some SDRAM defines.
This patch now changes lower case UIC defines to upper case. Also
some names are changed to match the naming in the IBM/AMCC users
manuals (e.g. mem_mcopt1 -> SDRAM0_CFG).

Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-28 10:45:54 +02:00
Stefan Roese
d1c3b27525 ppc4xx: Big cleanup of PPC4xx defines
This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:

- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
  user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines

Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-11 10:35:58 +02:00
Wolfgang Denk
1aada9cd64 Fix all linker scripts for older binutils versions (pre-2.16)
Commit f62fb99941 fixed handling of all rodata sections by using a
wildcard combined with calls to ld's builtin functions SORT_BY_ALIGNMENT()
and SORT_BY_NAME().  Unfortunately these functions were only
introduced with biunutils version 2.16, so the modification broke
building with all tool chains using older binutils.

This patch makes it work again.  This is done by omitting the use of
these functions for such old tool chains.  This will result in
slightly larger target binaries, as the rodata sections are no longer
in optimal order alignment-wise which reauls in unused gaps, but the
effect was found to be insignificant - especially compared to the fact
that you cannot build U-Boot at all in the current state.

As ld seems to have no support for conditionals we run the linker
script through the C preprocessor which can be easily used to remove
the unwanted function calls.

Note that the C preprocessor must be run with the "-ansi" (or a
"-std=") option to make sure all the system-specific predefined
macros outside the reserved namespace are suppressed. Otherise, cpp
might for example substitute "powerpc" to "1", thus corrupting for
example "OUTPUT_ARCH(powerpc)" etc.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
2009-08-21 23:13:34 +02:00
Mingkai Hu
269610f6ba NAND boot: fix nand_load overlap issue
The code copy data from NAND flash block by block, so when
the data length isn't a whole-number multiple of the block
size, it will overlap the rest space.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-08-21 22:55:47 +02:00
Stefan Roese
82a7edc7ea ppc4xx: Canyonlands-NAND-boot: Support 2 Crucial 512MByte SODIMM's
Some Canyonlands boards are equipped with different SODIMM's. This is no
problem with the "normal" NOR booting Canyonlands U-Boot, since it
automatically detects the SODIMM's via SPD data and correctly configures
them. But the NAND booting version is different. Here we only have 4k
of image size to completely setup the hardware, including DDR2 setup.
So we need to use a fixed DDR2 setup here. This doesn't work for different
SODIMM's right now.

Currently only this Crucial SODIMM is support:
CT6464AC667.8FB (dual ranked)

Now some boards are shipped with this SODIMM:
CT6464AC667.4FE (single ranked)

This patch now supports both SODIMM's by configuring first for the dual
ranked DIMM. A quick shows, if this module is really installed. If this test
fails, the DDR2 controller is re-configured for the single
ranked SODIMM.

Tested with those SODIMM's:

CT6464AC667.8FB (dual ranked)
CT6464AC667.4FE (single ranked)

Signed-off-by: Stefan Roese <sr@denx.de>
2009-07-30 07:22:18 +02:00
Stefan Roese
12582ac771 nand/ppc4xx: Move PPC4xx NAND driver to common NAND driver directory
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-07-16 17:52:02 -05:00
Scott Wood
1dac3a5187 nand_spl: Fix cmd_ctrl usage in nand_boot.c.
When adding large page NAND support to this file, I had a misunderstanding
about the exact semantics of NAND_CTRL_CHANGE (which isn't documented
anywhere I can find) -- it is apparently just a hint to drivers,
which aren't required to preserve the old value for subsequent
non-"change" invocations.

This change makes nand_boot.c no longer assume this.  Note that this
happened to work by chance with some NAND drivers, which don't preserve
the value, but treat 0 equivalently to NAND_CTRL_ALE.

I don't have hardware to test this, so any testing is appreciated.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-07-07 17:58:10 -05:00
Guennadi Liakhovetski
b74ab73736 nand_spl: read environment early, when booting from NAND using nand_spl
Currently, when booting from NAND using nand_spl, in the beginning the default
environment is used until later in boot process the dynamic environment is read
out. This way environment variables that must be interpreted early, like the
baudrate or "silent", cannot be modified dynamically and remain at their
default values. Fix this problem by reading out main and redundand (if used)
copies of the environment in the nand_spl code.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-07-07 17:58:07 -05:00
Magnus Lilja
d08e5ca301 MX31: Add NAND SPL boot support to i.MX31 PDK board.
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
2009-07-06 21:53:18 +02:00
Magnus Lilja
40c642bc19 MX31: Add NAND SPL for i.MX31.
This patch adds the NAND SPL framework needed to boot i.MX31 boards
from NAND.

It has been tested on a i.MX31 PDK board with large page NAND. Small
page NANDs should work as well, but this has not been tested.

Note: The i.MX31 NFC uses a non-standard layout for large page NANDs,
whether this is compatible with a particular setup depends on how
the NAND device is programmed by the flash programmer (e.g. JTAG
debugger).

The patch is based on the work by Maxim Artamonov.

Signed-off-by: Maxim Artamonov <scn1874@yandex.ru>
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
2009-06-21 16:18:12 +02:00
Detlev Zundel
792a09eb9d Fix e-mail address of Gary Jennejohn.
Signed-off-by: Detlev Zundel <dzu@denx.de>
2009-05-15 22:11:59 +02:00
Trent Piepho
f62fb99941 Fix all linker script to handle all rodata sections
A recent gcc added a new unaligned rodata section called '.rodata.str1.1',
which needs to be added the the linker script.  Instead of just adding this
one section, we use a wildcard ".rodata*" to get all rodata linker section
gcc has now and might add in the future.

However, '*(.rodata*)' by itself will result in sub-optimal section
ordering.  The sections will be sorted by object file, which causes extra
padding between the unaligned rodata.str.1.1 of one object file and the
aligned rodata of the next object file.  This is easy to fix by using the
SORT_BY_ALIGNMENT command.

This patch has not be tested one most of the boards modified.  Some boards
have a linker script that looks something like this:

*(.text)
. = ALIGN(16);
*(.rodata)
*(.rodata.str1.4)
*(.eh_frame)

I change this to:

*(.text)
. = ALIGN(16);
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))

This means the start of rodata will no longer be 16 bytes aligned.
However, the boundary between text and rodata/eh_frame is still aligned to
16 bytes, which is what I think the real purpose of the ALIGN call is.

Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
2009-03-20 22:39:12 +01:00
Wolfgang Denk
4b00d1aa82 SIMPC8313 board: fix out of tree building.
Fix typo in makefile which broke out of tree builds.

Also use expolicit "rm" instead of "ln -sf" which is known to be
unreliable.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-03-09 10:51:39 +01:00
Wolfgang Denk
c1b7c70083 Merge branch 'master' of git://git.denx.de/u-boot-nand-flash 2009-01-28 23:14:22 +01:00
Kim Phillips
2b6fd5c77d mpc83xx: fix undefined reference to `flush_cache' error in simpc8313 build
extend commit c70564e6b1
"NAND: Fix cache and memory inconsistency issue" to add the cache.o dependency
to the simpc8313 build and fix this:

...Large Page NAND...Configuring for SIMPC8313 board...
nand_boot_fsl_elbc.o: In function `nand_boot':
nand_spl/board/sheldon/simpc8313/nand_boot_fsl_elbc.c:150: undefined reference to `flush_cache'
make[1]: *** [/home/r1aaha/git/u-boot-mpc83xx/nand_spl/u-boot-spl] Error 1
make: *** [nand_spl] Error 2

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-01-28 10:00:56 +01:00
Stefan Roese
de832a9941 nand_spl: Fix compile problem with board_nand_init() prototype
This patch removes the now obsolete and additionally wrongly defined
board_nand_init() prototype from nand_spl/nand_boot.c.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-01-26 13:39:17 -06:00
Kim Phillips
833d94bcdc Merge branch 'next' 2009-01-23 17:48:24 -06:00
Ron Madrid
5bb907a492 mpc83xx: New board support for SIMPC8313
This patch will create a new board, SIMPC8313, from Sheldon Instruments.  This
board boots from NAND devices and is configureable for either large or small
page devices.  The board supports non-soldered DDR2, one ethernet port, a
Marvell 88E1118 PHY, and PCI host support.  The board also has a FPGA connected
to the eLBC providing glue logic to a TMS320C67xx DSP.

Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-01-23 11:31:18 -06:00
Dave Liu
c70564e6b1 NAND: Fix cache and memory inconsistency issue
We load the secondary stage u-boot image from NAND to
system memory by nand_load, but we did not flush d-cache
to memory, nor invalidate i-cache before we jump to RAM.
When the system has cache enabled and the TLB/page attribute
of system memory is cacheable, it will cause issues.

- 83xx family is using the d-cache lock, so all of d-cache
  access is cache-inhibited. so you can't see the issue.
- 85xx family is using d-cache, i-cache enable, partial
  cache lock. you will see the issue.

This patch fixes the cache issue.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-01-23 10:32:50 -06:00
Selvamuthukumar
9b827cf172 Align end of bss by 4 bytes
Most of the bss initialization loop increments 4 bytes
at a time. And the loop end is checked for an 'equal'
condition. Make the bss end address aligned by 4, so
that the loop will end as expected.

Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-11-18 23:13:16 +01:00
Haiying Wang
4e190b03aa Make Freescale local bus registers available for both 83xx and 85xx.
- Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it
  can be shared by both 83xx and 85xx
- Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards
  files which use lbus83xx_t.
- Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that
  85xx can share them.

Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-10-29 11:12:53 -05:00
Jean-Christophe PLAGNIOL-VILLARD
6d0f6bcf33 rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-18 21:54:03 +02:00
Guennadi Liakhovetski
11edcfe260 ARM: Add support for S3C6400 based SMDK6400 board
SMDK6400 can only boot U-Boot from NAND-flash. This patch adds a nand_spl
driver for it too. The board can also boot from the NOR flash, but due to
hardware limitations it can only address 64KiB on it, which is not enough
for U-Boot. Based on the original sources by Samsung for U-Boot 1.1.6.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
2008-08-31 00:39:47 +02:00
Scott Wood
8d765456c1 NAND: Remove delay from nand_boot_fsl_elbc.c.
It was for debugging purposes, and shouldn't have been left in.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-08-21 13:44:17 -05:00
Wolfgang Denk
4b0708093e Coding Style cleanup, update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-08-14 14:41:06 +02:00
Guennadi Liakhovetski
aa646643b6 nand_spl: Support page-aligned read in nand_load, use chipselect
Supporting page-aligned reads doesn't incure any sinificant overhead, just
a small change in the algorithm. Also replace in_8 with readb, since there
is no in_8 on ARM.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-08-12 11:31:32 -05:00
Scott Wood
4f32d7760a NAND boot: Update large page support for current API.
Also, remove the ctrl variable in favor of passing the constants
directly, and remove redundant (u8) casts.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-08-12 11:31:31 -05:00
Scott Wood
e4c0950854 NAND boot: MPC8313ERDB support
Note that with older board revisions, NAND boot may only work after a
power-on reset, and not after a warm reset.  I don't have a newer board
to test on; if you have a board with a 33MHz crystal, please let me know
if it works after a warm reset.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-08-12 11:31:31 -05:00
Stefan Roese
c568f77acd NAND: Update nand_spl driver to match updated nand subsystem
This patch changes the NAND booting driver nand_spl/nand_boot.c to match
the new infrastructure from the updated NAND subsystem. This NAND
subsystem was recently synced again with the Linux 2.6.22 MTD/NAND
subsystem.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-08-12 11:31:23 -05:00
Scott Wood
2dacb734ba NAND: $(obj)-qualify ecc.h in kilauea NAND boot Makefile.
This fixes building out-of-tree.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-07-30 00:37:08 +02:00
Becky Bruce
9973e3c614 Change initdram() return type to phys_size_t
This patch changes the return type of initdram() from long int to phys_size_t.
This is required for a couple of reasons: long int limits the amount of dram
to 2GB, and u-boot in general is moving over to phys_size_t to represent the
size of physical memory.  phys_size_t is defined as an unsigned long on almost
all current platforms.

This patch *only* changes the return type of the initdram function (in
include/common.h, as well as in each board's implementation of initdram).  It
does not actually modify the code inside the function on any of the platforms;
platforms which wish to support more than 2GB of DRAM will need to modify
their initdram() function code.

Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc
MPC8641HPCN.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-06-12 08:50:18 +02:00
Stefan Roese
63a0afa0c3 ppc4xx: Fix problem with SDRAM init in bamboo NAND booting port
This patch fixes a problem spotted by Eugene O'Brian (thanks Eugene)
introduced by the commit:

ppc4xx/NAND_SPL: Consolidate 405 and 440 NAND booting code in start.S

With this patch SDRAM will get initialized again and booting from NAND
is working again.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
2008-06-04 21:34:12 +02:00
Kenneth Johansson
2918eb9d42 Remove shell variable UNDEF_SYM.
UNDEF_SYM is a shell variable in the main Makefile used to force the
linker to add all u-boot commands to the final image. It has no use here.

Signed-off-by: Kenneth Johansson <kenneth@southpole.se>
2008-06-03 20:36:18 +02:00
Stefan Roese
ec724f883e ppc4xx: Change Kilauea to use the common DDR2 init function
This patch changes the kilauea and kilauea_nand (for NAND booting)
board port to not use a board specific DDR2 init routine anymore. Now
the common code from cpu/ppc4xx is used.

Thanks to Grant Erickson for all his basic work on this 405EX early
bootup.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-03 20:22:03 +02:00
Stefan Roese
64852d09e0 ppc4xx/NAND_SPL: Consolidate 405 and 440 NAND booting code in start.S
This patch consolidates the 405 and 440 parts of the NAND booting code
selected via CONFIG_NAND_SPL. Now common code is used to initialize the
SDRAM by calling initdram() and to "copy/relocate" to SDRAM/OCM/etc.
Only *after* running from this location, nand_boot() is called.

Please note that the initsdram() call is now moved from nand_boot.c
to start.S. I experienced problems with some boards like Kilauea
(405EX), which don't have internal SRAM (OCM) and relocation needs to
be done to SDRAM before the NAND controller can get accessed. When
initdram() is called later on in nand_boot(), this can lead to problems
with variables in the bss sections like nand_ecc_pos[].

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
2008-06-03 20:21:49 +02:00
Stefan Roese
fdd1247a66 ppc4xx: Individual handling of ddr2_fixed.c for canyonlands_nand build
Canyonlands has a file ddr2_fixed.c which needs special treatment when
building in separate directory. It has to be linked to build directory
otherwise it is not seen.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-05-14 12:26:16 +02:00
Stefan Roese
4f27098e5b ppc4xx: Adapt Canyonlands fixed DDR2 setup to new DIMM module
This patch changes the Canyonlands/Glacier fixed DDR2 controller setup
used for NAND booting to match the values needed for the new 512MB
DIMM modules shipped with the productions boards:

Crucial: CT6464AC667.8FB

Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-30 14:51:36 +02:00
Wolfgang Denk
926662762e Merge branch 'master' of git://www.denx.de/git/u-boot-nand-flash 2008-04-25 11:10:17 +02:00
Stefan Roese
499e7831e1 ppc4xx: Change Canyonlands to support booting from 2k page NAND devices
Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-18 16:30:49 +02:00
Stefan Roese
5e182dce04 ppc4xx: Adjust Canyonlands fixed DDR2 setup (NAND booting) to 512MB SODIMM
Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-18 16:30:39 +02:00