/*
 * Copyright (C) 2012 sysmocom s.f.m.c. GmbH
 * Author: Holger Hans Peter Freyther
 *
 * Copyright (C) 2009 Lyrtech RD Inc. <www.lyrtech.com>
 *
 * Based on dvevm/dvevm.c, original copyright follows:
 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
 *
 * Parts are shamelessly stolen from various TI sources, original copyright
 * follows:
 * -----------------------------------------------------------------
 *
 * Copyright (C) 2004 Texas Instruments.
 *
 * ----------------------------------------------------------------------------
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 * ----------------------------------------------------------------------------
 */

#include <common.h>
#include <i2c.h>
#include <asm/arch/hardware.h>
#include <asm/arch/davinci_misc.h>

#define DAVINCI_PLLM      (0x01C40910)	/* PLL 1 Multiplier */
#define DAVINCI_AWCCR     (0x01E00004)	/* EMIF-A async wait cycle config register. */
#define DAVINCI_AWCCR_VAL (0x000000FF)	/* EMIF-A async wait cycle config register value. */
#define DAVINCI_A1CR      (0x01E00010)	/* EMIF-A CS2 config register. */
#define DAVINCI_A1CR_VAL  (0x44502280)	/* EMIF-A CS2 value for NAND. */
#define DAVINCI_A1CR_VAL8 (0x44502280)	/* EMIF-A CS2 value for NAND. */
#define DAVINCI_A2CR      (0x01E00014)	/* EMIF-A CS3 config register. */
#define DAVINCI_A2CR_VAL  (0x00430491)	/* EMIF-A CS3 value for FPGA.  */
#define DAVINCI_A2CR_VAL8 (0x00630591)	/* EMIF-A CS3 value for FPGA.  */

DECLARE_GLOBAL_DATA_PTR;

static int get_board_revision(void)
{
	unsigned *gpio01 = (unsigned *)(DAVINCI_GPIO_BASE + 0x20);
	return (*gpio01 >> 15) & 0x0007;
}

/* Read ethernet MAC address from EEPROM.
 * Returns 1 if found, 0 otherwise.
 */
static int sysmobts_v2_read_mac_address(uint8_t *buf)
{
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
	/* Read MAC address. */
	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x0000, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
		     (uint8_t *) &buf[0], 6))
		goto i2cerr;

	/* Revision A, B, C (64LC02) or Revision D (64LC64) */
	if (get_board_revision() <= 2) {
		if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x0000, 1,
				(uint8_t *) &buf[0], 6))
			goto i2cerr;
	} else {
		if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x0000, 2,
				(uint8_t *) &buf[0], 6))
			goto i2cerr;
	}

	/* Check that MAC address is valid. */
	if (!is_valid_ether_addr(buf))
		goto err;

	return 1; /* Found */

i2cerr:
	printf("Read from EEPROM @ 0x%02x failed\n", CONFIG_SYS_I2C_EEPROM_ADDR);
err:
#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */

	return 0;
}

int board_init(void)
{
	/* arch number of the board */
	gd->bd->bi_arch_number = MACH_TYPE_SYSMOBTS_V2;

	/* address of boot parameters */
	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;

	/* Configure pins */
	REG(PINMUX0) = 0x8000000f;
	REG(PINMUX1) = 0x00050187;

	/* Configure AEMIF AWCCR */
	REG(DAVINCI_AWCCR) = DAVINCI_AWCCR_VAL;

	/* DM644X @ 594/297 MHz */
	if ( (REG(DAVINCI_PLLM) & 0x0FF) < 22 ) {

		/* Configure AEMIF CS2 (nand) */
		REG(DAVINCI_A1CR) = DAVINCI_A1CR_VAL;

		/* Configure AEMIF CS3 (fpga) */
		REG(DAVINCI_A2CR) = DAVINCI_A2CR_VAL;

	/* DM644X @ 810/405 MHz	*/
	} else {

		/* Configure AEMIF CS2 (nand) */
		REG(DAVINCI_A1CR) = DAVINCI_A1CR_VAL8;

		/* Configure AEMIF CS3 (fpga) */
		REG(DAVINCI_A2CR) = DAVINCI_A2CR_VAL8;
	}

	davinci_errata_workarounds();

	/* Power on required peripherals */
	lpsc_on(DAVINCI_LPSC_GPIO);

	/*
	 * U-Boot does not support more than one EEPROM and we need to
	 * set parameters depending on the actual hardware revision we
	 * run on.
	 * Revision A, B, C (64LC02), Revision D (64LC64)
	 */
	if (get_board_revision() <= 2) {
		eeprom_set_addr_len(1);
		eeprom_set_page_size(1 << 3);
	} else {
		eeprom_set_addr_len(2);
		eeprom_set_page_size(1 << 5);
	}

	/* Powerup the DSP */
	dsp_on();

	davinci_enable_uart0();
	davinci_enable_emac();
	davinci_enable_i2c();

	lpsc_on(DAVINCI_LPSC_TIMER1);
	timer_init();

	return(0);
}

int board_late_init(void)
{
#ifdef CONFIG_PREBOOT
	/* remember if we are in reset */
	if (gpio_get_value(38) == 0) {
		setenv("preboot", "run_recovery");
		status_led_set(0, STATUS_LED_ON);
	} else {
		/* configure LEDs */
		status_led_set(0, STATUS_LED_OFF);
	}
#endif
}

int misc_init_r(void)
{
	uint8_t eeprom_enetaddr[6];

	/* Read Ethernet MAC address from EEPROM if available. */
	if (sysmobts_v2_read_mac_address(eeprom_enetaddr))
		davinci_sync_env_enetaddr(eeprom_enetaddr);

	setenv("fwup", "dhcp;setenv filesize 0;tftp 85000000 ${tftp_serverip}:rootfs.ubi;mtdpart default;nand erase.part RootFs;nand write 85000000 100000 ${filesize}");
	return(0);
}