559 lines
17 KiB
C
559 lines
17 KiB
C
/*
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* Memory controller config:
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* Assumes that the caches are initialized.
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*
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* 0) Figah out the Tap controller settings.
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* 1) Figure out whether the interface is 16bit or 32bit.
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* 2) Size the DRAM
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*
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* 0) Tap controller settings
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* --------------------------
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* The Table below provides all possible values of TAP controllers. We need to
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* find the extreme left and extreme right of the spectrum (of max_udelay and
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* min_udelay). We then program the TAP to be in the middle.
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* Note for this we would need to be able to read and write memory. So,
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* initially we assume that a 16bit interface, which will always work unless
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* there is exactly _1_ 32 bit part...for now we assume this is not the case.
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*
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* The algo:
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* 0) Program the controller in 16bit mode.
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* 1) Start with the extreme left of the table
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* 2) Write 0xa4, 0xb5, 0xc6, 0xd7 to 0, 2, 4, 6
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* 3) Read 0 - this will fetch the entire cacheline.
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* 4) If the value at address 4 is good, record this table entry, goto 6
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* 5) Increment to get the next table entry. Goto 2.
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* 6) Start with extreme right. Do the same as above.
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*
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* 1) 16bit or 32bit
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* -----------------
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* 31st bit of reg 0x1800_0000 will determine the mode. By default,
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* controller is set to 32-bit mode. In 32 bit mode, full data bus DQ [31:0]
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* will be used to write 32 bit data. Suppose you have 16bit DDR memory
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* (it will have 16bit wide data bus). If you try to write 16 bit DDR in 32
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* bit mode, you are going to miss upper 16 bits of data. Reading to that
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* location will give you only lower 16 bits correctly, upper 16 bits will
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* have some junk value. E.g.,
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*
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* write to 0x0000_0000 0x12345678
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* write to 0x0000_1000 0x00000000 (just to discharge DQ[31:16] )
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* read from 0x0000_0000
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* if u see something like 0x0000_5678 (or XXXX_5678 but not equal to
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* 0x12345678) - its a 16 bit interface
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*
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* 2) Size the DRAM
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* -------------------
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* DDR wraps around. Write a pattern to 0x0000_0000. Write an address
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* pattern at 4M, 8M, 16M etc. and check when 0x0000_0000 gets overwritten.
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*
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*
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* We can use #define's for all these addresses and patterns but its easier
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* to see what's going on without :)
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*/
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#include <common.h>
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#include <asm/addrspace.h>
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#include "ar7240_soc.h"
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#ifdef COMPRESSED_UBOOT
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# define prmsg(...)
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#else
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# define prmsg debug
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#endif
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uint8_t tap_settings[] =
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{0x40, 0x41, 0x10, 0x12, 0x13, 0x15, 0x1a, 0x1c, 0x1f, 0x2f, 0x3f};
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uint16_t tap_pattern[] = {0xa5, 0xb6, 0xc7, 0xd8};
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void
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ar7240_ddr_tap_set(uint8_t set)
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{
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ar7240_reg_wr_nf(AR7240_DDR_TAP_CONTROL0, set);
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ar7240_reg_wr_nf(AR7240_DDR_TAP_CONTROL1, set);
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ar7240_reg_wr_nf(AR7240_DDR_TAP_CONTROL2, set);
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ar7240_reg_wr_nf(AR7240_DDR_TAP_CONTROL3, set);
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}
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/*
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* We check for size in 4M increments
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*/
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#define AR7240_DDR_SIZE_INCR (4*1024*1024)
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int
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ar7240_ddr_find_size(void)
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{
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uint8_t *p = (uint8_t *)KSEG1, pat = 0x77;
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int i;
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*p = pat;
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for(i = 1; ; i++) {
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*(p + i * AR7240_DDR_SIZE_INCR) = (uint8_t)(i);
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if (*p != pat) {
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break;
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}
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}
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return (i*AR7240_DDR_SIZE_INCR);
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}
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#ifndef CONFIG_WASP
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void
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ar7240_ddr_initial_config(uint32_t refresh)
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{
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int ddr2 = 0,ddr_config;
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int ddr_config2,ext_mod,ddr2_ext_mod;
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int mod_val,mod_val_init;
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prmsg("\nsri\n");
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#if 0
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ar7240_reg_wr(AR7240_RESET, AR7240_RESET_DDR);
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udelay(10);
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#endif
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ddr2 = ((ar7240_reg_rd(0xb8050020) & 0x1) == 0);
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#ifdef ENABLE_DYNAMIC_CONF
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if(*(volatile int *)CFG_DDR_MAGIC_F == CFG_DDR_MAGIC){
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ddr_config = CFG_DDR_CONFIG_VAL_F;
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ddr_config2 = CFG_DDR_CONFIG2_VAL_F;
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ext_mod = CFG_DDR_EXT_MODE_VAL_F;
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ddr2_ext_mod = ext_mod;
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}
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else
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#endif
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{
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#ifdef CONFIG_SUPPORT_AR7241
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if (is_ar7241() || is_ar7242()) {
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if (ddr2) {
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prmsg("%s(%d): virian ddr2 init\n", __func__, __LINE__);
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ddr_config = CFG_7241_DDR2_CONFIG_VAL;
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ddr_config2 = CFG_7241_DDR2_CONFIG2_VAL;
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ext_mod = CFG_7241_DDR2_EXT_MODE_VAL;
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ddr2_ext_mod = CFG_DDR2_EXT_MODE_VAL;
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mod_val_init = CFG_7241_DDR2_MODE_VAL_INIT;
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mod_val = CFG_7241_DDR2_MODE_VAL;
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} else {
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prmsg("%s(%d): virian ddr1 init\n", __func__, __LINE__);
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ddr_config = CFG_7241_DDR1_CONFIG_VAL;
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ddr_config2 = CFG_7241_DDR1_CONFIG2_VAL;
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ext_mod = CFG_7241_DDR1_EXT_MODE_VAL;
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ddr2_ext_mod = CFG_DDR2_EXT_MODE_VAL;
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mod_val_init = CFG_7241_DDR1_MODE_VAL_INIT;
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mod_val = CFG_7241_DDR1_MODE_VAL;
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}
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}
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else
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#endif
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{
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prmsg("%s(%d): python ddr init\n", __func__, __LINE__);
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ddr_config = CFG_DDR_CONFIG_VAL;
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ddr_config2 = CFG_DDR_CONFIG2_VAL;
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ext_mod = CFG_DDR_EXT_MODE_VAL;
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#ifndef CONFIG_WASP_EMU
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ddr2_ext_mod = CFG_DDR2_EXT_MODE_VAL;
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#endif
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mod_val_init = CFG_DDR_MODE_VAL_INIT;
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mod_val = CFG_DDR_MODE_VAL;
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}
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}
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if (ddr2) {
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ar7240_reg_wr_nf(0xb800008c, 0xA59);
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udelay(100);
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ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x10);
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udelay(10);
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ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x20);
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udelay(10);
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}
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ar7240_reg_wr_nf(AR7240_DDR_CONFIG, ddr_config);
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udelay(100);
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ar7240_reg_wr_nf(AR7240_DDR_CONFIG2, ddr_config2 | 0x80);
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udelay(100);
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ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x8);
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udelay(10);
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ar7240_reg_wr_nf(AR7240_DDR_MODE, mod_val_init);
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udelay(1000);
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ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x1);
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udelay(10);
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if (ddr2) {
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ar7240_reg_wr_nf(AR7240_DDR_EXT_MODE, ddr2_ext_mod);
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} else {
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ar7240_reg_wr_nf(AR7240_DDR_EXT_MODE, ext_mod);
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}
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udelay(100);
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ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x2);
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udelay(10);
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ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x8);
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udelay(10);
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ar7240_reg_wr_nf(AR7240_DDR_MODE, mod_val);
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udelay(100);
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ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x1);
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udelay(10);
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ar7240_reg_wr_nf(AR7240_DDR_REFRESH, refresh);
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udelay(100);
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ar7240_reg_wr_nf(AR7240_DDR_RD_DATA_THIS_CYCLE,
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CFG_DDR_RD_DATA_THIS_CYCLE_VAL);
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udelay(100);
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}
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#else
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int /* ram type */
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wasp_ddr_initial_config(uint32_t refresh)
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{
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#if !defined(CONFIG_ATH_NAND_BR)
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int ddr_config, ddr_config2, ext_mod, mod_val,
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mod_val_init, cycle_val, tap_val, type;
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uint32_t *pll = (unsigned *)PLL_CONFIG_VAL_F;
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prmsg("\nsri\n");
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prmsg("Wasp 1.%d\n", ar7240_reg_rd(AR7240_REV_ID) & 0xf);
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switch(WASP_RAM_TYPE(ar7240_reg_rd(WASP_BOOTSTRAP_REG))) {
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case 0:
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case 1: // SDRAM
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/*
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XXX XXX XXX XXX XXX XXX XXX XXX XXX
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Boot strap select is not working. In some boards,
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ddr2 shows up as sdram. Hence ignoring the foll.
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break statement.
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XXX XXX XXX XXX XXX XXX XXX XXX XXX
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break;
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*/
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prmsg("%s(%d): Wasp sdram\n", __func__, __LINE__);
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ddr_config = CFG_934X_SDRAM_CONFIG_VAL;
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ddr_config2 = CFG_934X_SDRAM_CONFIG2_VAL;
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mod_val_init = CFG_934X_SDRAM_MODE_VAL_INIT;
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mod_val = CFG_934X_SDRAM_MODE_VAL;
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cycle_val = CFG_SDRAM_RD_DATA_THIS_CYCLE_VAL;
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tap_val = CFG_934X_SDRAM_TAP_VAL;
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ar7240_reg_wr_nf(AR7240_DDR_CTL_CONFIG, 0x13b);
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udelay(100);
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ar7240_reg_wr_nf(AR7240_DDR_DEBUG_RD_CNTL, 0x3000001f);
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udelay(100);
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type = 0;
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break;
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case 2: // ddr2
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ddr_config = CFG_934X_DDR2_CONFIG_VAL;
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ddr_config2 = CFG_934X_DDR2_CONFIG2_VAL;
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ext_mod = CFG_934X_DDR2_EXT_MODE_VAL;
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mod_val_init = CFG_934X_DDR2_MODE_VAL_INIT;
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mod_val = CFG_934X_DDR2_MODE_VAL;
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cycle_val = CFG_DDR2_RD_DATA_THIS_CYCLE_VAL;
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tap_val = CFG_934X_DDR2_TAP_VAL;
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prmsg("%s(%d): (", __func__, __LINE__);
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if (ar7240_reg_rd(AR7240_REV_ID) & 0xf) {
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/* NAND Clear */
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if (ar7240_reg_rd(WASP_BOOTSTRAP_REG) & (1 << 3)) {
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prmsg("32");
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cycle_val = CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32;
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ar7240_reg_wr_nf(AR7240_DDR_CTL_CONFIG, (1 << 6));
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} else {
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prmsg("16");
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cycle_val = CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16;
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ar7240_reg_rmw_set(AR7240_DDR_CTL_CONFIG, (1 << 6));
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ar7240_reg_rmw_clear(AR7240_DDR_CTL_CONFIG, (0xf << 2));
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}
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} else {
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#if DDR2_32BIT_SUPPORT
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prmsg("32");
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ar7240_reg_wr_nf(AR7240_DDR_CTL_CONFIG, 0);
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#else
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prmsg("16");
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#endif
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}
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prmsg("bit) ddr2 init\n");
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udelay(10);
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type = 1;
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break;
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case 3: // ddr1
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prmsg("%s(%d): Wasp (16bit) ddr1 init\n", __func__, __LINE__);
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ddr_config = CFG_934X_DDR1_CONFIG_VAL;
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ddr_config2 = CFG_934X_DDR1_CONFIG2_VAL;
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ext_mod = CFG_934X_DDR1_EXT_MODE_VAL;
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mod_val_init = CFG_934X_DDR1_MODE_VAL_INIT;
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mod_val = CFG_934X_DDR1_MODE_VAL;
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cycle_val = CFG_DDR1_RD_DATA_THIS_CYCLE_VAL;
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tap_val = CFG_934X_DDR1_TAP_VAL;
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type = 2;
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break;
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}
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#if 0
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if (*pll == PLL_MAGIC) {
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uint32_t cas = pll[5];
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if (cas == 3 || cas == 4) {
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cas = (cas * 2) + 1;
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ddr_config &= ~(DDR_CONFIG_CAS_LATENCY_MSB_MASK |
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DDR_CONFIG_CAS_LATENCY_MASK);
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ddr_config |= DDR_CONFIG_CAS_LATENCY_SET(cas & 0x7) |
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DDR_CONFIG_CAS_LATENCY_MSB_SET((cas >> 3) & 1);
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cas = pll[5];
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ddr_config2 &= ~DDR_CONFIG2_GATE_OPEN_LATENCY_MASK;
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ddr_config2 |= DDR_CONFIG2_GATE_OPEN_LATENCY_SET(2 * cas);
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if (type == 1) {
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uint32_t tmp;
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tmp = ar7240_reg_rd(AR7240_DDR_DDR2_CONFIG);
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tmp &= ~DDR2_CONFIG_DDR2_TWL_MASK;
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tmp |= DDR2_CONFIG_DDR2_TWL_SET(cas == 3 ? 3 : 5);
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ar7240_reg_wr_nf(AR7240_DDR_DDR2_CONFIG, tmp);
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}
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mod_val = (cas == 3 ? 0x33 : 0x43);
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mod_val_init = 0x100 | mod_val;
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}
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}
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#else
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if (*pll == PLL_MAGIC) {
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uint32_t cas = pll[5];
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if (cas == 3 || cas == 4) {
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cas = (cas * 2) + 2;
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ddr_config &= ~(DDR_CONFIG_CAS_LATENCY_MSB_MASK |
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DDR_CONFIG_CAS_LATENCY_MASK);
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ddr_config |= DDR_CONFIG_CAS_LATENCY_SET(cas & 0x7) |
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DDR_CONFIG_CAS_LATENCY_MSB_SET((cas >> 3) & 1);
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cas = pll[5];
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ddr_config2 &= ~DDR_CONFIG2_GATE_OPEN_LATENCY_MASK;
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ddr_config2 |= DDR_CONFIG2_GATE_OPEN_LATENCY_SET((2 * cas) + 1);
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if (type == 1) {
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uint32_t tmp;
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tmp = ar7240_reg_rd(AR7240_DDR_DDR2_CONFIG);
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tmp &= ~DDR2_CONFIG_DDR2_TWL_MASK;
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tmp |= DDR2_CONFIG_DDR2_TWL_SET(cas == 3 ? 3 : 5);
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ar7240_reg_wr_nf(AR7240_DDR_DDR2_CONFIG, tmp);
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}
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mod_val = (cas == 3 ? 0x33 : 0x43);
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mod_val_init = 0x100 | mod_val;
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}
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}
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#endif
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ar7240_reg_wr_nf(AR7240_DDR_RD_DATA_THIS_CYCLE, cycle_val);
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udelay(100);
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ar7240_reg_wr_nf(AR7240_DDR_BURST, 0x74444444);
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udelay(100);
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ar7240_reg_wr_nf(AR7240_DDR_BURST2, 0x222);
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udelay(100);
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ar7240_reg_wr_nf(AR7240_AHB_MASTER_TIMEOUT, 0xfffff);
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udelay(100);
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ar7240_reg_wr_nf(AR7240_DDR_CONFIG, ddr_config);
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udelay(100);
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ar7240_reg_wr_nf(AR7240_DDR_CONFIG2, ddr_config2);
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udelay(100);
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if (type == 1) {
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ar7240_reg_wr_nf(AR7240_DDR_DDR2_CONFIG, CFG_934X_DDR2_EN_TWL_VAL);
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udelay(100);
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}
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ar7240_reg_wr_nf(AR7240_DDR_CONFIG2, ddr_config2 | 0x80); // CKE enable
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udelay(100);
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ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x8); // Precharge
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udelay(10);
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ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x8); // Precharge
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udelay(10);
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if (type == 1) {
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ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x10); // EMR2
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udelay(10);
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ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x20); // EMR3
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udelay(10);
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}
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if (type != 0) {
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ar7240_reg_wr_nf(AR7240_DDR_EXT_MODE, 0x2);
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udelay(100);
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ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x2); // EMR DLL enable
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udelay(10);
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}
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ar7240_reg_wr_nf(AR7240_DDR_MODE, mod_val_init);
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udelay(1000);
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ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x1); // MR Write
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udelay(10);
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ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x8); // Precharge
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udelay(10);
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ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x8); // Precharge
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udelay(10);
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ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x4); // Auto Refresh
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udelay(10);
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ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x4); // Auto Refresh
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udelay(10);
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ar7240_reg_wr_nf(AR7240_DDR_MODE, mod_val);
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udelay(100);
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ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x1); // MR Write
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udelay(10);
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if (type == 1) {
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ar7240_reg_wr_nf(AR7240_DDR_EXT_MODE, CFG_934X_DDR2_EXT_MODE_VAL_INIT);
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udelay(100);
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ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x2); // EMR write
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udelay(100);
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ar7240_reg_wr_nf(AR7240_DDR_EXT_MODE, CFG_934X_DDR2_EXT_MODE_VAL);
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udelay(100);
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ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x2); // EMR write
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udelay(100);
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}
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ar7240_reg_wr_nf(AR7240_DDR_REFRESH, refresh);
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udelay(100);
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ar7240_reg_wr (AR7240_DDR_TAP_CONTROL0, tap_val);
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ar7240_reg_wr (AR7240_DDR_TAP_CONTROL1, tap_val);
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if (ar7240_reg_rd(AR7240_REV_ID) & 0xf) {
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/* NAND Clear */
|
|
if ((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & (1 << 3)) && type) {
|
|
ar7240_reg_wr (AR7240_DDR_TAP_CONTROL2, tap_val);
|
|
ar7240_reg_wr (AR7240_DDR_TAP_CONTROL3, tap_val);
|
|
}
|
|
} else {
|
|
#if DDR2_32BIT_SUPPORT
|
|
if (type != 0) {
|
|
ar7240_reg_wr (AR7240_DDR_TAP_CONTROL2, tap_val);
|
|
ar7240_reg_wr (AR7240_DDR_TAP_CONTROL3, tap_val);
|
|
}
|
|
#endif
|
|
}
|
|
prmsg("%s(%d): Wasp ddr init done\n", __func__, __LINE__);
|
|
|
|
#if (CFG_PLL_FREQ == CFG_PLL_600_500_250) || \
|
|
(CFG_PLL_FREQ == CFG_PLL_500_500_250)
|
|
// PMU2 ddr ldo tune
|
|
ar7240_reg_rmw_set(0xb8116c44, (0x3 << 19));
|
|
udelay(100);
|
|
#endif
|
|
return type;
|
|
#else
|
|
return 0;
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_HORNET_EMU
|
|
void
|
|
ar7240_ddr_initial_config_for_fpga(void)
|
|
{
|
|
#ifdef CONFIG_HORNET_EMU_HARDI
|
|
/* HARDI FPGA board */
|
|
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x4); /* Auto-Refresh */
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_REFRESH, 0x4100);
|
|
udelay(10);
|
|
|
|
ar7240_reg_wr_nf(AR7240_DDR_CONFIG, 0x7fd68cd0); /* Cas Latency 7 */
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_CONFIG2, 0x959ec6a8); /* Gate Open 5 */
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_DDR2_CONFIG, 0x858); /* Disable DDR2, set Write Latency */
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x8); /* precharge all */
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x8); /* precharge all */
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x1); /* MR update */
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_MODE, 0x133); /* Mode Word Settings */
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_EXT_MODE, 0x0); /* Extended Mode Word Settings */
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_RD_DATA_THIS_CYCLE, 0xff); /* DDR read data capture bit mask */
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x1); /* MR update */
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x2); /* EMR update */
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x8); /* precharge all */
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x8); /* precharge all */
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x4); /* Auto-Refresh */
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x4); /* Auto-Refresh */
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_MODE, 0x133); /* Mode Word Settings */
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x1); /* MR update */
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_EXT_MODE, 0x382); /* Extended Mode Word Settings */
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x2); /* EMR update */
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_EXT_MODE, 0x402); /* Extended Mode Word Settings */
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x2); /* EMR update */
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_MODE, 0x33); /* Mode Word Settings */
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x1); /* MR update */
|
|
udelay(10);
|
|
#ifdef CONFIG_HORNET_EMU_HARDI_WLAN
|
|
/*
|
|
* Emulation board reference clock is 48 MHz(20.833ns)
|
|
* DDR request 64ms has 8192 refresh
|
|
* So each refresh interval is 64ms/8192 = 7812.5 ns
|
|
* i.e ddr have to refresh in 7812.5/20.833 = 375 = 0x177 clock cycles
|
|
*/
|
|
ar7240_reg_wr_nf(AR7240_DDR_REFRESH, 0x4177);
|
|
#else
|
|
/*
|
|
* Emulation board reference clock is 80 MHz(12.5ns)
|
|
* DDR request 64ms has 8192 refresh
|
|
* So each refresh interval is 64ms/8192 = 7812.5 ns
|
|
* i.e ddr have to refresh in 7812.5/12.5 = 625 = 0x271 clock cycles
|
|
*/
|
|
ar7240_reg_wr_nf(AR7240_DDR_REFRESH, 0x4271);
|
|
#endif
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_TAP_CONTROL0, 0x0);
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_TAP_CONTROL1, 0x0);
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_TAP_CONTROL2, 0x0);
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_TAP_CONTROL3, 0x0);
|
|
udelay(10);
|
|
#else
|
|
/* EBU FPGA board */
|
|
ar7240_reg_wr_nf(AR7240_DDR_CONFIG, 0xc7bc8cd0); /* Cas Latency 8 */
|
|
udelay(100);
|
|
ar7240_reg_wr_nf(AR7240_DDR_CONFIG2, 0x95d0e6a8); /* Gate Open 5 */
|
|
udelay(100);
|
|
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x8);
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_MODE, 0x123);
|
|
udelay(100);
|
|
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x1);
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_EXT_MODE, 0x1);
|
|
udelay(100);
|
|
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x2);
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x8);
|
|
udelay(10);
|
|
ar7240_reg_wr_nf(AR7240_DDR_MODE, 0x23);
|
|
udelay(100);
|
|
ar7240_reg_wr_nf(AR7240_DDR_CONTROL, 0x1);
|
|
udelay(10);
|
|
/*
|
|
* Emulation board reference clock is 80 MHz(12.5ns)
|
|
* DDR request 64ms has 8192 refresh
|
|
* So each refresh interval is 64ms/8192 = 7812.5 ns
|
|
* i.e ddr have to refresh in 7812.5/12.5 = 625 = 0x271 clock cycles
|
|
*/
|
|
ar7240_reg_wr_nf(AR7240_DDR_REFRESH, 0x4271);
|
|
udelay(100);
|
|
ar7240_reg_wr_nf(AR7240_DDR_RD_DATA_THIS_CYCLE, 0x00ff);
|
|
udelay(100);
|
|
#endif
|
|
}
|
|
#endif
|