u-boot

History

Shaohui Xie 145dbc0250 powerpc/p2041: configure the CPLD lane_mux according to RCW Lane muxing on p2041 is controlled by a reg in CPLD, offset of this reg is 0xc, CPLD supports SATA by default, we should re-configure the lane muxing according to RCW, which indicates what SerDes protocol it is running. Default lane muxing map is as below: Lane G on bank1 routes to SGMII, controlled by bit 1 of the reg; Lane A on bank2 routes to AURORA, controlled by bit 0 of the reg; Lane C/D on bank2 routes to SATA0 and SATA1, controlled by bit 2 and bit 3 respectively. Default value of these bits for lane muxing is '1', we should set or clear these bits accoring to RCW. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>		2012-08-08 17:13:39 -05:00
..
Makefile	punt unused clean/distclean targets	2011-10-15 22:20:36 +02:00
README	doc: cleanup - move board READMEs into respective board directories	2012-07-29 15:42:02 +02:00
cpld.c	powerpc/p2041rdb: remove watch dog related codes	2011-10-03 08:52:13 -05:00
cpld.h	powerpc/p2041rdb: remove watch dog related codes	2011-10-03 08:52:13 -05:00
ddr.c	powerpc/mpc8xxx: Merge entries in DDR speed table	2011-10-09 17:57:53 -05:00
eth.c	powerpc/p2041: configure the CPLD lane_mux according to RCW	2012-08-08 17:13:39 -05:00
p2041rdb.c	powerpc/85xx: Add USB device-tree fixup for various platforms	2012-07-06 17:03:25 -05:00

README

Overview
=========
The P2041 Processor combines four Power Architecture processor cores
with high-performance datapath acceleration architecture(DPAA), CoreNet
fabric infrastructure, as well as network and peripheral bus interfaces
required for networking, telecom/datacom, wireless infrastructure, and
military/aerospace applications.

P2041RDB board is a quad core platform supporting the P2041 processor
of QorIQ DPAA series.

Boot from NOR flash
===================
1. Build image
	make P2041RDB_config
	make all

2. Program image
	=> tftp 1000000 u-boot.bin
	=> protect off all
	=> erase eff80000 efffffff
	=> cp.b 1000000 eff80000 80000

3. Program RCW
	=> tftp 1000000 rcw.bin
	=> protect off all
	=> erase e8000000 e801ffff
	=> cp.b 1000000 e8000000 50

4. Program FMAN Firmware ucode
	=> tftp 1000000 ucode.bin
	=> protect off all
	=> erase ef000000 ef0fffff
	=> cp.b 1000000 ef000000 2000

5. Change DIP-switch
	SW1[1-5] = 10110
	Note: 1 stands for 'on', 0 stands for 'off'

Boot from SDCard
===================
1. Build image
	make P2041RDB_SDCARD_config
	make all

2. Generate PBL imge
   Use PE tool to produce a image used to be programed to
   SDCard which contains RCW and U-Boot image.

3. Program the PBL image to SDCard
	=> tftp 1000000 pbl_sd.bin
	=> mmcinfo
	=> mmc write 1000000 8 441

4. Program FMAN Firmware ucode
	=> tftp 1000000 ucode.bin
	=> mmc write 1000000 46a 10

5. Change DIP-switch
	SW1[1-5] = 01100
	Note: 1 stands for 'on', 0 stands for 'off'

Boot from SPI flash
===================
1. Build image
	make P2041RDB_SPIFLASH_config
	make all

2. Generate PBL imge
   Use PE tool to produce a image used to be programed to
   SPI flash which contains RCW and U-Boot image.

3. Program the PBL image to SPI flash
	=> tftp 1000000 pbl_spi.bin
	=> spi probe 0
	=> sf erase 0 100000
	=> sf write 1000000 0 $filesize

4. Program FMAN Firmware ucode
	=> tftp 1000000 ucode.bin
	=> sf erase 110000 10000
	=> sf write 1000000 110000 $filesize

5. Change DIP-switch
	SW1[1-5] = 10100
	Note: 1 stands for 'on', 0 stands for 'off'

CPLD command
============
The CPLD is used to control the power sequence and some serdes lane
mux function.

cpld reset			 - hard reset to default bank
cpld reset altbank		 - reset to alternate bank
cpld lane_mux <lane> <mux_value> - set multiplexed lane pin
		lane 6: 0 -> slot1 (Default)
			1 -> SGMII
		lane a: 0 -> slot2 (Default)
			1 -> AURORA
		lane c: 0 -> slot2 (Default)
			1 -> SATA0
		lane d: 0 -> slot2 (Default)
			1 -> SATA1

Using the Device Tree Source File
=================================
To create the DTB (Device Tree Binary) image file, use a command
similar to this:
	dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb

Or use the following command:
	{linux-2.6}/make p2041rdb.dtb ARCH=powerpc

then the dtb file will be generated under the following directory:
	{linux-2.6}/arch/powerpc/boot/p2041rdb.dtb

Booting Linux
=============
Place a linux uImage in the TFTP disk area.
	tftp 1000000 uImage
	tftp 2000000 rootfs.ext2.gz.uboot
	tftp 3000000 p2041rdb.dtb
	bootm 1000000 2000000 3000000