u-boot/board/freescale/mpc8548cds
chenhui zhao 568336ecc7 powerpc/mpc85xxcds: Fix PCI speed
The CDS uses PCICLK as SYSCLK. The PCICLK should be 33333333Hz or 66666666Hz.

Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com>
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-03 08:52:14 -05:00
..
Makefile Switch from archive libraries to partial linking 2010-11-17 21:02:18 +01:00
ddr.c powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from board 2011-04-04 09:24:41 -05:00
law.c powerpc/85xx: Convert MPC8548CDS to use common SRIO init code 2011-01-14 01:32:21 -06:00
mpc8548cds.c powerpc/mpc85xxcds: Fix PCI speed 2011-10-03 08:52:14 -05:00
tlb.c powerpc/85xx: Convert MPC8548CDS to use common SRIO init code 2011-01-14 01:32:21 -06:00