chenhui zhao 568336ecc7 powerpc/mpc85xxcds: Fix PCI speed ... The CDS uses PCICLK as SYSCLK. The PCICLK should be 33333333Hz or 66666666Hz. Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>		2011-10-03 08:52:14 -05:00
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Makefile	Switch from archive libraries to partial linking	2010-11-17 21:02:18 +01:00
ddr.c	powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from board	2011-04-04 09:24:41 -05:00
law.c	rename CFG_ macros to CONFIG_SYS	2008-10-18 21:54:03 +02:00
mpc8555cds.c	powerpc/mpc85xxcds: Fix PCI speed	2011-10-03 08:52:14 -05:00
tlb.c	85xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boards	2009-01-23 17:03:13 -06:00