All mx6 based boards should use arch_cpu_init(). Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
144 lines
3.7 KiB
C
144 lines
3.7 KiB
C
/*
|
|
* (C) Copyright 2007
|
|
* Sascha Hauer, Pengutronix
|
|
*
|
|
* (C) Copyright 2009 Freescale Semiconductor, Inc.
|
|
*
|
|
* See file CREDITS for list of people who contributed to this
|
|
* project.
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of
|
|
* the License, or (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
* MA 02111-1307 USA
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/errno.h>
|
|
#include <asm/io.h>
|
|
#include <asm/arch/imx-regs.h>
|
|
#include <asm/arch/clock.h>
|
|
#include <asm/arch/sys_proto.h>
|
|
|
|
u32 get_cpu_rev(void)
|
|
{
|
|
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
|
|
int reg = readl(&anatop->digprog);
|
|
|
|
/* Read mx6 variant: quad, dual or solo */
|
|
int system_rev = (reg >> 4) & 0xFF000;
|
|
/* Read mx6 silicon revision */
|
|
system_rev |= (reg & 0xFF) + 0x10;
|
|
|
|
return system_rev;
|
|
}
|
|
|
|
void init_aips(void)
|
|
{
|
|
struct aipstz_regs *aips1, *aips2;
|
|
|
|
aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
|
|
aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
|
|
|
|
/*
|
|
* Set all MPROTx to be non-bufferable, trusted for R/W,
|
|
* not forced to user-mode.
|
|
*/
|
|
writel(0x77777777, &aips1->mprot0);
|
|
writel(0x77777777, &aips1->mprot1);
|
|
writel(0x77777777, &aips2->mprot0);
|
|
writel(0x77777777, &aips2->mprot1);
|
|
|
|
/*
|
|
* Set all OPACRx to be non-bufferable, not require
|
|
* supervisor privilege level for access,allow for
|
|
* write access and untrusted master access.
|
|
*/
|
|
writel(0x00000000, &aips1->opacr0);
|
|
writel(0x00000000, &aips1->opacr1);
|
|
writel(0x00000000, &aips1->opacr2);
|
|
writel(0x00000000, &aips1->opacr3);
|
|
writel(0x00000000, &aips1->opacr4);
|
|
writel(0x00000000, &aips2->opacr0);
|
|
writel(0x00000000, &aips2->opacr1);
|
|
writel(0x00000000, &aips2->opacr2);
|
|
writel(0x00000000, &aips2->opacr3);
|
|
writel(0x00000000, &aips2->opacr4);
|
|
}
|
|
|
|
/*
|
|
* Set the VDDSOC
|
|
*
|
|
* Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
|
|
* them to the specified millivolt level.
|
|
* Possible values are from 0.725V to 1.450V in steps of
|
|
* 0.025V (25mV).
|
|
*/
|
|
void set_vddsoc(u32 mv)
|
|
{
|
|
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
|
|
u32 val, reg = readl(&anatop->reg_core);
|
|
|
|
if (mv < 725)
|
|
val = 0x00; /* Power gated off */
|
|
else if (mv > 1450)
|
|
val = 0x1F; /* Power FET switched full on. No regulation */
|
|
else
|
|
val = (mv - 700) / 25;
|
|
|
|
/*
|
|
* Mask out the REG_CORE[22:18] bits (REG2_TRIG)
|
|
* and set them to the calculated value (0.7V + val * 0.25V)
|
|
*/
|
|
reg = (reg & ~(0x1F << 18)) | (val << 18);
|
|
writel(reg, &anatop->reg_core);
|
|
}
|
|
|
|
int arch_cpu_init(void)
|
|
{
|
|
init_aips();
|
|
|
|
set_vddsoc(1200); /* Set VDDSOC to 1.2V */
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifndef CONFIG_SYS_DCACHE_OFF
|
|
void enable_caches(void)
|
|
{
|
|
/* Enable D-cache. I-cache is already enabled in start.S */
|
|
dcache_enable();
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_FEC_MXC)
|
|
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
|
|
{
|
|
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
|
|
struct fuse_bank *bank = &iim->bank[4];
|
|
struct fuse_bank4_regs *fuse =
|
|
(struct fuse_bank4_regs *)bank->fuse_regs;
|
|
|
|
u32 value = readl(&fuse->mac_addr_high);
|
|
mac[0] = (value >> 8);
|
|
mac[1] = value ;
|
|
|
|
value = readl(&fuse->mac_addr_low);
|
|
mac[2] = value >> 24 ;
|
|
mac[3] = value >> 16 ;
|
|
mac[4] = value >> 8 ;
|
|
mac[5] = value ;
|
|
|
|
}
|
|
#endif
|