No need to Unlock DPLL initially. DDR3 can work at normal OPP from initialozation Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
599 lines
16 KiB
C
599 lines
16 KiB
C
/*
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*
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* Clock initialization for OMAP4
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*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Aneesh V <aneesh@ti.com>
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*
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* Based on previous work by:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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* Rajendra Nayak <rnayak@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/omap_common.h>
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#include <asm/gpio.h>
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#include <asm/arch/clocks.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/utils.h>
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#include <asm/omap_gpio.h>
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#ifndef CONFIG_SPL_BUILD
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/*
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* printing to console doesn't work unless
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* this code is executed from SPL
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*/
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#define printf(fmt, args...)
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#define puts(s)
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#endif
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static inline u32 __get_sys_clk_index(void)
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{
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u32 ind;
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/*
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* For ES1 the ROM code calibration of sys clock is not reliable
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* due to hw issue. So, use hard-coded value. If this value is not
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* correct for any board over-ride this function in board file
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* From ES2.0 onwards you will get this information from
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* CM_SYS_CLKSEL
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*/
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if (omap_revision() == OMAP4430_ES1_0)
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ind = OMAP_SYS_CLK_IND_38_4_MHZ;
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else {
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/* SYS_CLKSEL - 1 to match the dpll param array indices */
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ind = (readl(&prcm->cm_sys_clksel) &
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CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
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}
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return ind;
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}
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u32 get_sys_clk_index(void)
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__attribute__ ((weak, alias("__get_sys_clk_index")));
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u32 get_sys_clk_freq(void)
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{
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u8 index = get_sys_clk_index();
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return sys_clk_array[index];
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}
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static inline void do_bypass_dpll(u32 *const base)
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{
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struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
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clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
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CM_CLKMODE_DPLL_DPLL_EN_MASK,
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DPLL_EN_FAST_RELOCK_BYPASS <<
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CM_CLKMODE_DPLL_EN_SHIFT);
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}
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static inline void wait_for_bypass(u32 *const base)
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{
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struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
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if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
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LDELAY)) {
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printf("Bypassing DPLL failed %p\n", base);
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}
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}
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static inline void do_lock_dpll(u32 *const base)
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{
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struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
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clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
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CM_CLKMODE_DPLL_DPLL_EN_MASK,
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DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
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}
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static inline void wait_for_lock(u32 *const base)
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{
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struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
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if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
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&dpll_regs->cm_idlest_dpll, LDELAY)) {
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printf("DPLL locking failed for %p\n", base);
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hang();
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}
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}
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inline u32 check_for_lock(u32 *const base)
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{
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struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
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u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
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return lock;
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}
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static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
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u8 lock, char *dpll)
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{
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u32 temp, M, N;
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struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
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temp = readl(&dpll_regs->cm_clksel_dpll);
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if (check_for_lock(base)) {
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/*
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* The Dpll has already been locked by rom code using CH.
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* Check if M,N are matching with Ideal nominal opp values.
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* If matches, skip the rest otherwise relock.
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*/
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M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
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N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
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if ((M != (params->m)) || (N != (params->n))) {
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debug("\n %s Dpll locked, but not for ideal M = %d,"
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"N = %d values, current values are M = %d,"
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"N= %d" , dpll, params->m, params->n,
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M, N);
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} else {
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/* Dpll locked with ideal values for nominal opps. */
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debug("\n %s Dpll already locked with ideal"
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"nominal opp values", dpll);
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goto setup_post_dividers;
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}
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}
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bypass_dpll(base);
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/* Set M & N */
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temp &= ~CM_CLKSEL_DPLL_M_MASK;
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temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
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temp &= ~CM_CLKSEL_DPLL_N_MASK;
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temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
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writel(temp, &dpll_regs->cm_clksel_dpll);
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/* Lock */
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if (lock)
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do_lock_dpll(base);
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setup_post_dividers:
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setup_post_dividers(base, params);
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/* Wait till the DPLL locks */
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if (lock)
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wait_for_lock(base);
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}
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u32 omap_ddr_clk(void)
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{
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u32 ddr_clk, sys_clk_khz, omap_rev, divider;
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const struct dpll_params *core_dpll_params;
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omap_rev = omap_revision();
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sys_clk_khz = get_sys_clk_freq() / 1000;
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core_dpll_params = get_core_dpll_params();
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debug("sys_clk %d\n ", sys_clk_khz * 1000);
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/* Find Core DPLL locked frequency first */
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ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
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(core_dpll_params->n + 1);
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if (omap_rev < OMAP5430_ES1_0) {
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/*
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* DDR frequency is PHY_ROOT_CLK/2
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* PHY_ROOT_CLK = Fdpll/2/M2
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*/
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divider = 4;
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} else {
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/*
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* DDR frequency is PHY_ROOT_CLK
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* PHY_ROOT_CLK = Fdpll/2/M2
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*/
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divider = 2;
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}
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ddr_clk = ddr_clk / divider / core_dpll_params->m2;
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ddr_clk *= 1000; /* convert to Hz */
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debug("ddr_clk %d\n ", ddr_clk);
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return ddr_clk;
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}
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/*
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* Lock MPU dpll
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*
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* Resulting MPU frequencies:
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* 4430 ES1.0 : 600 MHz
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* 4430 ES2.x : 792 MHz (OPP Turbo)
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* 4460 : 920 MHz (OPP Turbo) - DCC disabled
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*/
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void configure_mpu_dpll(void)
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{
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const struct dpll_params *params;
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struct dpll_regs *mpu_dpll_regs;
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u32 omap_rev;
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omap_rev = omap_revision();
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/*
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* DCC and clock divider settings for 4460.
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* DCC is required, if more than a certain frequency is required.
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* For, 4460 > 1GHZ.
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* 5430 > 1.4GHZ.
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*/
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if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
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mpu_dpll_regs =
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(struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu;
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bypass_dpll(&prcm->cm_clkmode_dpll_mpu);
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clrbits_le32(&prcm->cm_mpu_mpu_clkctrl,
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MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
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setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
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MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
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clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
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CM_CLKSEL_DCC_EN_MASK);
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}
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setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
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MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
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setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
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MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
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params = get_mpu_dpll_params();
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do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
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debug("MPU DPLL locked\n");
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}
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#ifdef CONFIG_USB_EHCI_OMAP
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static void setup_usb_dpll(void)
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{
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const struct dpll_params *params;
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u32 sys_clk_khz, sd_div, num, den;
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sys_clk_khz = get_sys_clk_freq() / 1000;
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/*
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* USB:
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* USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
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* DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
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* - where CLKINP is sys_clk in MHz
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* Use CLKINP in KHz and adjust the denominator accordingly so
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* that we have enough accuracy and at the same time no overflow
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*/
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params = get_usb_dpll_params();
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num = params->m * sys_clk_khz;
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den = (params->n + 1) * 250 * 1000;
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num += den - 1;
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sd_div = num / den;
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clrsetbits_le32(&prcm->cm_clksel_dpll_usb,
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CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
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sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
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/* Now setup the dpll with the regular function */
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do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
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}
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#endif
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static void setup_dplls(void)
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{
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u32 temp;
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const struct dpll_params *params;
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debug("setup_dplls\n");
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/* CORE dpll */
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params = get_core_dpll_params(); /* default - safest */
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/*
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* Do not lock the core DPLL now. Just set it up.
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* Core DPLL will be locked after setting up EMIF
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* using the FREQ_UPDATE method(freq_update_core())
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*/
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if (omap_revision() != OMAP5432_ES1_0)
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do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
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DPLL_NO_LOCK, "core");
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else
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do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
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DPLL_LOCK, "core");
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/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
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temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
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(CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
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(CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
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writel(temp, &prcm->cm_clksel_core);
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debug("Core DPLL configured\n");
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/* lock PER dpll */
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params = get_per_dpll_params();
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do_setup_dpll(&prcm->cm_clkmode_dpll_per,
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params, DPLL_LOCK, "per");
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debug("PER DPLL locked\n");
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/* MPU dpll */
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configure_mpu_dpll();
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#ifdef CONFIG_USB_EHCI_OMAP
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setup_usb_dpll();
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#endif
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}
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#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
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static void setup_non_essential_dplls(void)
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{
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u32 abe_ref_clk;
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const struct dpll_params *params;
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/* IVA */
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clrsetbits_le32(&prcm->cm_bypclk_dpll_iva,
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CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
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params = get_iva_dpll_params();
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do_setup_dpll(&prcm->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
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/* Configure ABE dpll */
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params = get_abe_dpll_params();
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#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
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abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
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#else
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abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
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/*
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* We need to enable some additional options to achieve
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* 196.608MHz from 32768 Hz
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*/
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setbits_le32(&prcm->cm_clkmode_dpll_abe,
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CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
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CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
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CM_CLKMODE_DPLL_LPMODE_EN_MASK|
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CM_CLKMODE_DPLL_REGM4XEN_MASK);
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/* Spend 4 REFCLK cycles at each stage */
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clrsetbits_le32(&prcm->cm_clkmode_dpll_abe,
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CM_CLKMODE_DPLL_RAMP_RATE_MASK,
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1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
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#endif
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/* Select the right reference clk */
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clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel,
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CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
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abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
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/* Lock the dpll */
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do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
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}
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#endif
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void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv)
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{
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u32 step;
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int ret = 0;
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/* See if we can first get the GPIO if needed */
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if (gpio >= 0)
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ret = gpio_request(gpio, "TPS62361_VSEL0_GPIO");
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if (ret < 0) {
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printf("%s: gpio %d request failed %d\n", __func__, gpio, ret);
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gpio = -1;
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}
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/* Pull the GPIO low to select SET0 register, while we program SET1 */
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if (gpio >= 0)
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gpio_direction_output(gpio, 0);
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step = volt_mv - TPS62361_BASE_VOLT_MV;
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step /= 10;
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debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step);
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if (omap_vc_bypass_send_value(TPS62361_I2C_SLAVE_ADDR, reg, step))
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puts("Scaling voltage failed for vdd_mpu from TPS\n");
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/* Pull the GPIO high to select SET1 register */
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if (gpio >= 0)
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gpio_direction_output(gpio, 1);
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}
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void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
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{
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u32 offset_code;
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u32 offset = volt_mv;
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/* convert to uV for better accuracy in the calculations */
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offset *= 1000;
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offset_code = get_offset_code(offset);
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debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
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offset_code);
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if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR,
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vcore_reg, offset_code))
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printf("Scaling voltage failed for 0x%x\n", vcore_reg);
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}
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static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
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{
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clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
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enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
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debug("Enable clock domain - %p\n", clkctrl_reg);
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}
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static inline void wait_for_clk_enable(u32 *clkctrl_addr)
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{
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u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
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u32 bound = LDELAY;
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while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
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(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
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clkctrl = readl(clkctrl_addr);
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idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
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MODULE_CLKCTRL_IDLEST_SHIFT;
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if (--bound == 0) {
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printf("Clock enable failed for 0x%p idlest 0x%x\n",
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clkctrl_addr, clkctrl);
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return;
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}
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}
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}
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static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
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u32 wait_for_enable)
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{
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clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
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enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
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debug("Enable clock module - %p\n", clkctrl_addr);
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if (wait_for_enable)
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wait_for_clk_enable(clkctrl_addr);
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}
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void freq_update_core(void)
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{
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u32 freq_config1 = 0;
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const struct dpll_params *core_dpll_params;
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u32 omap_rev = omap_revision();
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core_dpll_params = get_core_dpll_params();
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/* Put EMIF clock domain in sw wakeup mode */
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enable_clock_domain(&prcm->cm_memif_clkstctrl,
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CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
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wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
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wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
|
|
|
|
freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
|
|
SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
|
|
|
|
freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
|
|
SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
|
|
|
|
freq_config1 |= (core_dpll_params->m2 <<
|
|
SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
|
|
SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
|
|
|
|
writel(freq_config1, &prcm->cm_shadow_freq_config1);
|
|
if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
|
|
&prcm->cm_shadow_freq_config1, LDELAY)) {
|
|
puts("FREQ UPDATE procedure failed!!");
|
|
hang();
|
|
}
|
|
|
|
/*
|
|
* Putting EMIF in HW_AUTO is seen to be causing issues with
|
|
* EMIF clocks and the master DLL. Put EMIF in SW_WKUP
|
|
* in OMAP5430 ES1.0 silicon
|
|
*/
|
|
if (omap_rev != OMAP5430_ES1_0) {
|
|
/* Put EMIF clock domain back in hw auto mode */
|
|
enable_clock_domain(&prcm->cm_memif_clkstctrl,
|
|
CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
|
|
wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
|
|
wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
|
|
}
|
|
}
|
|
|
|
void bypass_dpll(u32 *const base)
|
|
{
|
|
do_bypass_dpll(base);
|
|
wait_for_bypass(base);
|
|
}
|
|
|
|
void lock_dpll(u32 *const base)
|
|
{
|
|
do_lock_dpll(base);
|
|
wait_for_lock(base);
|
|
}
|
|
|
|
void setup_clocks_for_console(void)
|
|
{
|
|
/* Do not add any spl_debug prints in this function */
|
|
clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
|
|
CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
|
|
CD_CLKCTRL_CLKTRCTRL_SHIFT);
|
|
|
|
/* Enable all UARTs - console will be on one of them */
|
|
clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl,
|
|
MODULE_CLKCTRL_MODULEMODE_MASK,
|
|
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
|
|
MODULE_CLKCTRL_MODULEMODE_SHIFT);
|
|
|
|
clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl,
|
|
MODULE_CLKCTRL_MODULEMODE_MASK,
|
|
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
|
|
MODULE_CLKCTRL_MODULEMODE_SHIFT);
|
|
|
|
clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
|
|
MODULE_CLKCTRL_MODULEMODE_MASK,
|
|
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
|
|
MODULE_CLKCTRL_MODULEMODE_SHIFT);
|
|
|
|
clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
|
|
MODULE_CLKCTRL_MODULEMODE_MASK,
|
|
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
|
|
MODULE_CLKCTRL_MODULEMODE_SHIFT);
|
|
|
|
clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
|
|
CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
|
|
CD_CLKCTRL_CLKTRCTRL_SHIFT);
|
|
}
|
|
|
|
void do_enable_clocks(u32 *const *clk_domains,
|
|
u32 *const *clk_modules_hw_auto,
|
|
u32 *const *clk_modules_explicit_en,
|
|
u8 wait_for_enable)
|
|
{
|
|
u32 i, max = 100;
|
|
|
|
/* Put the clock domains in SW_WKUP mode */
|
|
for (i = 0; (i < max) && clk_domains[i]; i++) {
|
|
enable_clock_domain(clk_domains[i],
|
|
CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
|
|
}
|
|
|
|
/* Clock modules that need to be put in HW_AUTO */
|
|
for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
|
|
enable_clock_module(clk_modules_hw_auto[i],
|
|
MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
|
|
wait_for_enable);
|
|
};
|
|
|
|
/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
|
|
for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
|
|
enable_clock_module(clk_modules_explicit_en[i],
|
|
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
|
|
wait_for_enable);
|
|
};
|
|
|
|
/* Put the clock domains in HW_AUTO mode now */
|
|
for (i = 0; (i < max) && clk_domains[i]; i++) {
|
|
enable_clock_domain(clk_domains[i],
|
|
CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
|
|
}
|
|
}
|
|
|
|
void prcm_init(void)
|
|
{
|
|
switch (omap_hw_init_context()) {
|
|
case OMAP_INIT_CONTEXT_SPL:
|
|
case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
|
|
case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
|
|
enable_basic_clocks();
|
|
scale_vcores();
|
|
setup_dplls();
|
|
#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
|
|
setup_non_essential_dplls();
|
|
enable_non_essential_clocks();
|
|
#endif
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
|
|
enable_basic_uboot_clocks();
|
|
}
|