Convert this function over to use the driver model PCI API. In this case we want to avoid using the real PCI devices since they have not yet been probed. Instead, write directly to their PCI configuration address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
266 lines
6.4 KiB
C
266 lines
6.4 KiB
C
/*
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* Copyright (c) 2014 Google, Inc
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* (C) Copyright 2008
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* Graeme Russ, graeme.russ@gmail.com.
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*
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* Some portions from coreboot src/mainboard/google/link/romstage.c
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* and src/cpu/intel/model_206ax/bootblock.c
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* Copyright (C) 2007-2010 coresystems GmbH
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* Copyright (C) 2011 Google Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <pch.h>
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#include <asm/cpu.h>
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#include <asm/io.h>
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#include <asm/lapic.h>
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#include <asm/msr.h>
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#include <asm/mtrr.h>
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#include <asm/pci.h>
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#include <asm/post.h>
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#include <asm/processor.h>
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#include <asm/arch/model_206ax.h>
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#include <asm/arch/microcode.h>
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#include <asm/arch/pch.h>
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#include <asm/arch/sandybridge.h>
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DECLARE_GLOBAL_DATA_PTR;
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static int set_flex_ratio_to_tdp_nominal(void)
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{
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msr_t flex_ratio, msr;
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u8 nominal_ratio;
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/* Minimum CPU revision for configurable TDP support */
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if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
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return -EINVAL;
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/* Check for Flex Ratio support */
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flex_ratio = msr_read(MSR_FLEX_RATIO);
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if (!(flex_ratio.lo & FLEX_RATIO_EN))
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return -EINVAL;
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/* Check for >0 configurable TDPs */
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msr = msr_read(MSR_PLATFORM_INFO);
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if (((msr.hi >> 1) & 3) == 0)
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return -EINVAL;
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/* Use nominal TDP ratio for flex ratio */
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msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
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nominal_ratio = msr.lo & 0xff;
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/* See if flex ratio is already set to nominal TDP ratio */
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if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
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return 0;
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/* Set flex ratio to nominal TDP ratio */
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flex_ratio.lo &= ~0xff00;
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flex_ratio.lo |= nominal_ratio << 8;
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flex_ratio.lo |= FLEX_RATIO_LOCK;
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msr_write(MSR_FLEX_RATIO, flex_ratio);
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/* Set flex ratio in soft reset data register bits 11:6 */
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clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6,
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(nominal_ratio & 0x3f) << 6);
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/* Set soft reset control to use register value */
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setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1);
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/* Issue warm reset, will be "CPU only" due to soft reset data */
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outb(0x0, PORT_RESET);
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outb(SYS_RST | RST_CPU, PORT_RESET);
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cpu_hlt();
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/* Not reached */
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return -EINVAL;
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}
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int arch_cpu_init(void)
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{
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post_code(POST_CPU_INIT);
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return x86_cpu_init_f();
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}
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int arch_cpu_init_dm(void)
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{
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struct pci_controller *hose;
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struct udevice *bus, *dev;
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int ret;
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post_code(0x70);
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ret = uclass_get_device(UCLASS_PCI, 0, &bus);
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post_code(0x71);
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if (ret)
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return ret;
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post_code(0x72);
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hose = dev_get_uclass_priv(bus);
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/* TODO(sjg@chromium.org): Get rid of gd->hose */
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gd->hose = hose;
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ret = uclass_first_device(UCLASS_LPC, &dev);
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if (!dev)
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return -ENODEV;
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/*
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* We should do as little as possible before the serial console is
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* up. Perhaps this should move to later. Our next lot of init
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* happens in print_cpuinfo() when we have a console
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*/
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ret = set_flex_ratio_to_tdp_nominal();
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if (ret)
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return ret;
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return 0;
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}
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#define PCH_EHCI0_TEMP_BAR0 0xe8000000
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#define PCH_EHCI1_TEMP_BAR0 0xe8000400
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#define PCH_XHCI_TEMP_BAR0 0xe8001000
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/*
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* Setup USB controller MMIO BAR to prevent the reference code from
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* resetting the controller.
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*
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* The BAR will be re-assigned during device enumeration so these are only
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* temporary.
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*
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* This is used to speed up the resume path.
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*/
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static void enable_usb_bar(struct udevice *bus)
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{
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pci_dev_t usb0 = PCH_EHCI1_DEV;
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pci_dev_t usb1 = PCH_EHCI2_DEV;
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pci_dev_t usb3 = PCH_XHCI_DEV;
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ulong cmd;
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/* USB Controller 1 */
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pci_bus_write_config(bus, usb0, PCI_BASE_ADDRESS_0,
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PCH_EHCI0_TEMP_BAR0, PCI_SIZE_32);
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pci_bus_read_config(bus, usb0, PCI_COMMAND, &cmd, PCI_SIZE_32);
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cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_bus_write_config(bus, usb0, PCI_COMMAND, cmd, PCI_SIZE_32);
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/* USB Controller 2 */
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pci_bus_write_config(bus, usb1, PCI_BASE_ADDRESS_0,
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PCH_EHCI1_TEMP_BAR0, PCI_SIZE_32);
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pci_bus_read_config(bus, usb1, PCI_COMMAND, &cmd, PCI_SIZE_32);
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cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_bus_write_config(bus, usb1, PCI_COMMAND, cmd, PCI_SIZE_32);
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/* USB3 Controller 1 */
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pci_bus_write_config(bus, usb3, PCI_BASE_ADDRESS_0,
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PCH_XHCI_TEMP_BAR0, PCI_SIZE_32);
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pci_bus_read_config(bus, usb3, PCI_COMMAND, &cmd, PCI_SIZE_32);
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cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_bus_write_config(bus, usb3, PCI_COMMAND, cmd, PCI_SIZE_32);
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}
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static int report_bist_failure(void)
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{
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if (gd->arch.bist != 0) {
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post_code(POST_BIST_FAILURE);
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printf("BIST failed: %08x\n", gd->arch.bist);
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return -EFAULT;
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}
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return 0;
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}
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int print_cpuinfo(void)
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{
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enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE;
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char processor_name[CPU_MAX_NAME_LEN];
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struct udevice *dev, *lpc;
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const char *name;
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uint32_t pm1_cnt;
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uint16_t pm1_sts;
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int ret;
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/* Halt if there was a built in self test failure */
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ret = report_bist_failure();
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if (ret)
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return ret;
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enable_lapic();
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ret = microcode_update_intel();
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if (ret)
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return ret;
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/* Enable upper 128bytes of CMOS */
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writel(1 << 2, RCB_REG(RC));
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/* TODO: cmos_post_init() */
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if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) {
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debug("soft reset detected\n");
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boot_mode = PEI_BOOT_SOFT_RESET;
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/* System is not happy after keyboard reset... */
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debug("Issuing CF9 warm reset\n");
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reset_cpu(0);
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}
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/* Early chipset init required before RAM init can work */
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uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
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ret = uclass_first_device(UCLASS_LPC, &lpc);
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if (ret)
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return ret;
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if (!dev)
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return -ENODEV;
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/* Cause the SATA device to do its early init */
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uclass_first_device(UCLASS_DISK, &dev);
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/* Check PM1_STS[15] to see if we are waking from Sx */
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pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
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/* Read PM1_CNT[12:10] to determine which Sx state */
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pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
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if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
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debug("Resume from S3 detected, but disabled.\n");
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} else {
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/*
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* TODO: An indication of life might be possible here (e.g.
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* keyboard light)
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*/
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}
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post_code(POST_EARLY_INIT);
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/* Enable SPD ROMs and DDR-III DRAM */
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ret = uclass_first_device(UCLASS_I2C, &dev);
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if (ret)
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return ret;
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if (!dev)
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return -ENODEV;
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/* Prepare USB controller early in S3 resume */
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if (boot_mode == PEI_BOOT_RESUME)
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enable_usb_bar(pci_get_controller(lpc->parent));
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gd->arch.pei_boot_mode = boot_mode;
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/* Print processor name */
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name = cpu_get_name(processor_name);
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printf("CPU: %s\n", name);
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post_code(POST_CPU_INFO);
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return 0;
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}
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void board_debug_uart_init(void)
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{
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/* This enables the debug UART */
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pci_x86_write_config(NULL, PCH_LPC_DEV, LPC_EN, COMA_LPC_EN,
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PCI_SIZE_16);
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}
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