The do_lowlevel_init() function includes certian CA15 specific L2 cache configuration which is only applicable on Exynos5420 and members of its family. Fix the regression on Origen4210 by skipping the Exynos5420 specific portions of the code. Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Tested-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
228 lines
5.2 KiB
C
228 lines
5.2 KiB
C
/*
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* Lowlevel setup for EXYNOS5 based board
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*
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* Copyright (C) 2013 Samsung Electronics
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* Rajeshwari Shinde <rajeshwari.s@samsung.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <config.h>
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#include <debug_uart.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/dmc.h>
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#include <asm/arch/power.h>
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#include <asm/arch/tzpc.h>
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#include <asm/arch/periph.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/system.h>
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#include <asm/armv7.h>
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#include "common_setup.h"
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#include "exynos5_setup.h"
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/* These are the things we can do during low-level init */
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enum {
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DO_WAKEUP = 1 << 0,
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DO_CLOCKS = 1 << 1,
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DO_MEM_RESET = 1 << 2,
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DO_UART = 1 << 3,
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DO_POWER = 1 << 4,
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};
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#ifdef CONFIG_EXYNOS5420
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/*
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* Power up secondary CPUs.
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*/
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static void secondary_cpu_start(void)
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{
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v7_enable_smp(EXYNOS5420_INFORM_BASE);
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svc32_mode_en();
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branch_bx(CONFIG_EXYNOS_RELOCATE_CODE_BASE);
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}
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/*
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* This is the entry point of hotplug-in and
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* cluster switching.
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*/
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static void low_power_start(void)
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{
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uint32_t val, reg_val;
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reg_val = readl(EXYNOS5420_SPARE_BASE);
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if (reg_val != CPU_RST_FLAG_VAL) {
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writel(0x0, CONFIG_LOWPOWER_FLAG);
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branch_bx(0x0);
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}
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reg_val = readl(CONFIG_PHY_IRAM_BASE + 0x4);
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if (reg_val != (uint32_t)&low_power_start) {
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/* Store jump address as low_power_start if not present */
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writel((uint32_t)&low_power_start, CONFIG_PHY_IRAM_BASE + 0x4);
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dsb();
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sev();
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}
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/* Set the CPU to SVC32 mode */
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svc32_mode_en();
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#ifndef CONFIG_SYS_L2CACHE_OFF
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/* Read MIDR for Primary Part Number */
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mrc_midr(val);
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val = (val >> 4);
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val &= 0xf;
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if (val == 0xf) {
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configure_l2_ctlr();
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configure_l2_actlr();
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v7_enable_l2_hazard_detect();
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}
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#endif
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/* Invalidate L1 & TLB */
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val = 0x0;
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mcr_tlb(val);
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mcr_icache(val);
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/* Disable MMU stuff and caches */
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mrc_sctlr(val);
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val &= ~((0x2 << 12) | 0x7);
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val |= ((0x1 << 12) | (0x8 << 8) | 0x2);
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mcr_sctlr(val);
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/* CPU state is hotplug or reset */
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secondary_cpu_start();
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/* Core should not enter into WFI here */
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wfi();
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}
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/*
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* Pointer to this function is stored in iRam which is used
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* for jump and power down of a specific core.
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*/
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static void power_down_core(void)
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{
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uint32_t tmp, core_id, core_config;
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/* Get the unique core id */
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/*
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* Multiprocessor Affinity Register
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* [11:8] Cluster ID
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* [1:0] CPU ID
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*/
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mrc_mpafr(core_id);
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tmp = core_id & 0x3;
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core_id = (core_id >> 6) & ~3;
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core_id |= tmp;
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core_id &= 0x3f;
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/* Set the status of the core to low */
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core_config = (core_id * CPU_CONFIG_STATUS_OFFSET);
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core_config += EXYNOS5420_CPU_CONFIG_BASE;
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writel(0x0, core_config);
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/* Core enter WFI */
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wfi();
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}
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/*
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* Configurations for secondary cores are inapt at this stage.
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* Reconfigure secondary cores. Shutdown and change the status
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* of all cores except the primary core.
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*/
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static void secondary_cores_configure(void)
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{
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/* Clear secondary boot iRAM base */
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writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C));
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/* set lowpower flag and address */
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writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG);
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writel((uint32_t)&low_power_start, CONFIG_LOWPOWER_ADDR);
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writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE);
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/* Store jump address for power down */
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writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4);
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/* Need all core power down check */
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dsb();
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sev();
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}
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extern void relocate_wait_code(void);
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#endif
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int do_lowlevel_init(void)
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{
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uint32_t reset_status;
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int actions = 0;
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arch_cpu_init();
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#if !defined(CONFIG_SYS_L2CACHE_OFF) && defined(CONFIG_EXYNOS5420)
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/*
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* Init L2 cache parameters here for use by boot and resume
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*
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* These are here instead of in v7_outer_cache_enable() so that the
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* L2 cache settings get properly set even at resume time or if we're
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* running U-Boot with the cache off. The kernel still needs us to
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* set these for it.
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*/
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configure_l2_ctlr();
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configure_l2_actlr();
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dsb();
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isb();
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relocate_wait_code();
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/* Reconfigure secondary cores */
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secondary_cores_configure();
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#endif
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reset_status = get_reset_status();
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switch (reset_status) {
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case S5P_CHECK_SLEEP:
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actions = DO_CLOCKS | DO_WAKEUP;
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break;
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case S5P_CHECK_DIDLE:
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case S5P_CHECK_LPA:
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actions = DO_WAKEUP;
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break;
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default:
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/* This is a normal boot (not a wake from sleep) */
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actions = DO_CLOCKS | DO_MEM_RESET | DO_POWER;
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}
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if (actions & DO_POWER)
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set_ps_hold_ctrl();
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if (actions & DO_CLOCKS) {
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system_clock_init();
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#ifdef CONFIG_DEBUG_UART
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exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
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debug_uart_init();
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#endif
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mem_ctrl_init(actions & DO_MEM_RESET);
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tzpc_init();
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}
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return actions & DO_WAKEUP;
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}
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