Exception handling is basically identical for all ARM targets. Factorize it out of the various start.S files and into a single vectors.S file, and adjust linker scripts accordingly. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
54 lines
1.1 KiB
ArmAsm
54 lines
1.1 KiB
ArmAsm
/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <version.h>
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/* Save the parameter pass in by previous boot loader */
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.global save_boot_params
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save_boot_params:
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/* no parameter to save */
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bx lr
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/* Set up the platform, once the cpu has been initialized */
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.globl lowlevel_init
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lowlevel_init:
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/* Remap */
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#ifdef CONFIG_SPL_BUILD
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/*
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* SPL : configure the remap (L3 NIC-301 GPV)
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* so the on-chip RAM at lower memory instead ROM.
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*/
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ldr r0, =SOCFPGA_L3REGS_ADDRESS
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mov r1, #0x19
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str r1, [r0]
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#else
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/*
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* U-Boot : configure the remap (L3 NIC-301 GPV)
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* so the SDRAM at lower memory instead on-chip RAM.
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*/
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ldr r0, =SOCFPGA_L3REGS_ADDRESS
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mov r1, #0x2
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str r1, [r0]
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/* Private components security */
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/*
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* U-Boot : configure private timer, global timer and cpu
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* component access as non secure for kernel stage (as required
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* by kernel)
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*/
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mrc p15,4,r0,c15,c0,0
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add r1, r0, #0x54
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ldr r2, [r1]
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orr r2, r2, #0xff
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orr r2, r2, #0xf00
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str r2, [r1]
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#endif /* #ifdef CONFIG_SPL_BUILD */
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mov pc, lr
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