96 lines
2.8 KiB
C
96 lines
2.8 KiB
C
/*
|
|
* Copyright (C) 2009 Lyrtech RD Inc. <www.lyrtech.com>
|
|
*
|
|
* Based on dvevm/dvevm.c, original copyright follows:
|
|
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
|
*
|
|
* Parts are shamelessly stolen from various TI sources, original copyright
|
|
* follows:
|
|
* -----------------------------------------------------------------
|
|
*
|
|
* Copyright (C) 2004 Texas Instruments.
|
|
*
|
|
* ----------------------------------------------------------------------------
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
* (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
|
* ----------------------------------------------------------------------------
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <i2c.h>
|
|
#include <asm/arch/hardware.h>
|
|
#include <asm/arch/davinci_misc.h>
|
|
|
|
#define DAVINCI_AWCCR (0x01E00004) /* EMIF-A async wait cycle config register. */
|
|
#define DAVINCI_AWCCR_VAL (0x000000FF) /* EMIF-A async wait cycle config register value. */
|
|
#define DAVINCI_A1CR (0x01E00010) /* EMIF-A CS2 config register. */
|
|
#define DAVINCI_A1CR_VAL (0x44502280) /* EMIF-A CS2 value for NAND. */
|
|
#define DAVINCI_A2CR (0x01E00014) /* EMIF-A CS3 config register. */
|
|
#define DAVINCI_A2CR_VAL (0x00430491) /* EMIF-A CS3 value for FPGA. */
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
int board_init(void)
|
|
{
|
|
/* arch number of the board */
|
|
gd->bd->bi_arch_number = MACH_TYPE_FEMTOBTS;
|
|
|
|
/* address of boot parameters */
|
|
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
|
|
|
|
/* Configure pins */
|
|
REG(PINMUX0) = 0x80000c1f;
|
|
REG(PINMUX1) = 0x00050183;
|
|
|
|
/* Configure AEMIF AWCCR */
|
|
REG(DAVINCI_AWCCR) = DAVINCI_AWCCR_VAL;
|
|
|
|
/* Configure AEMIF CS2 (nand) */
|
|
REG(DAVINCI_A1CR) = DAVINCI_A1CR_VAL;
|
|
|
|
/* Configure AEMIF CS3 (fpga) */
|
|
REG(DAVINCI_A2CR) = DAVINCI_A2CR_VAL;
|
|
|
|
davinci_errata_workarounds();
|
|
|
|
/* Power on required peripherals */
|
|
lpsc_on(DAVINCI_LPSC_GPIO);
|
|
|
|
#if !defined(CONFIG_SYS_USE_DSPLINK)
|
|
/* Powerup the DSP */
|
|
dsp_on();
|
|
#endif /* CONFIG_SYS_USE_DSPLINK */
|
|
|
|
davinci_enable_uart0();
|
|
davinci_enable_emac();
|
|
davinci_enable_i2c();
|
|
|
|
lpsc_on(DAVINCI_LPSC_TIMER1);
|
|
timer_init();
|
|
|
|
return(0);
|
|
}
|
|
|
|
int misc_init_r(void)
|
|
{
|
|
uint8_t eeprom_enetaddr[6];
|
|
|
|
/* Read Ethernet MAC address from EEPROM if available. */
|
|
if (dvevm_read_mac_address(eeprom_enetaddr))
|
|
davinci_sync_env_enetaddr(eeprom_enetaddr);
|
|
|
|
return(0);
|
|
}
|
|
|