142 lines
3.9 KiB
C
142 lines
3.9 KiB
C
/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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* Dave Liu <daveliu@freescale.com>
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*
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* Copyright (C) 2007 Logic Product Development, Inc.
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* Peter Barada <peterb@logicpd.com>
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*
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* Copyright (C) 2007 MontaVista Software, Inc.
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* (C) Copyright 2008
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* (C) Copyright 2010-2011
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* Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_TUDA1 /* TUDA1 board specific */
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#define CONFIG_HOSTNAME tuda1
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#define CONFIG_KM_BOARD_NAME "tuda1"
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#define CONFIG_SYS_TEXT_BASE 0xF0000000
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/* include common defines/options for all 8321 Keymile boards */
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#include "km/km8321-common.h"
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#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */
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#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
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#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */
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#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2)
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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/*
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* Init Local Bus Memory Controller:
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*
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* Bank Bus Machine PortSz Size Device
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* ---- --- ------- ------ ----- ------
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* 2 Local GPCM 8 bit 256MB PAXG
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* 3 Local GPCM 8 bit 256MB PINC3
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*
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*/
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/*
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* PAXG on the local bus CS2
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*/
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/* Window base at flash base */
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#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE
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/* Window size: 256 MB */
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#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
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#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \
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BR_PS_8 | \
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BR_MS_GPCM | \
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BR_V)
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#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
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OR_GPCM_CSNT | \
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OR_GPCM_ACS_DIV4 | \
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OR_GPCM_SCY_2 | \
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(OR_GPCM_TRLX & \
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(~OR_GPCM_EHTR)) | /* EHTR = 0 */ \
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OR_GPCM_EAD)
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/*
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* PINC3 on the local bus CS3
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*/
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/* Access window base at PINC3 base */
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#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
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/* Window size: 256 MB */
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#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
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#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
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BR_PS_8 | \
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BR_MS_GPCM | \
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BR_V)
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#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
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OR_GPCM_CSNT | \
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(OR_GPCM_ACS_DIV2 & /* ACS = 11 */\
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(~OR_GPCM_XACS)) | /* XACS = 0 */\
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(OR_GPCM_SCY_2 & \
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(~OR_GPCM_EHTR)) | /* EHTR = 0 */ \
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OR_GPCM_TRLX)
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#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
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0x0000c000 | \
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MxMR_WLFx_2X)
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/*
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* MMU Setup
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*/
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/* PAXG: icache cacheable, but dcache-inhibit and guarded */
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#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \
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BATL_PP_10 | \
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BATL_MEMCOHERENCE)
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/* 512M should also include APP2... */
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#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \
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BATU_BL_256M | \
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BATU_VS | \
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BATU_VP)
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#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \
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BATL_PP_10 | \
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BATL_CACHEINHIBIT | \
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BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
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/* PINC3: icache cacheable, but dcache-inhibit and guarded */
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#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \
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BATL_PP_10 | \
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BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \
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BATU_BL_256M | \
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BATU_VS | \
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BATU_VP)
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#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \
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BATL_PP_10 | \
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BATL_CACHEINHIBIT | \
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BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
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#define CONFIG_SYS_IBAT7L (0)
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#define CONFIG_SYS_IBAT7U (0)
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#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
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#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
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#endif /* __CONFIG_H */
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