u-boot/board/jse
Becky Bruce 9973e3c614 Change initdram() return type to phys_size_t
This patch changes the return type of initdram() from long int to phys_size_t.
This is required for a couple of reasons: long int limits the amount of dram
to 2GB, and u-boot in general is moving over to phys_size_t to represent the
size of physical memory.  phys_size_t is defined as an unsigned long on almost
all current platforms.

This patch *only* changes the return type of the initdram function (in
include/common.h, as well as in each board's implementation of initdram).  It
does not actually modify the code inside the function on any of the platforms;
platforms which wish to support more than 2GB of DRAM will need to modify
their initdram() function code.

Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc
MPC8641HPCN.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-06-12 08:50:18 +02:00
..
config.mk * Patch by Stephen Williams, 01 Apr 2004: 2004-04-15 23:14:49 +00:00
flash.c Patch by Stephen Williams, 11 May 2004: 2004-06-09 00:15:33 +00:00
host_bridge.c * Code cleanup, mostly for GCC-3.3.x 2004-12-31 09:32:47 +00:00
init.S ppc4xx: Remove superfluous dram_init() call or replace it by initdram() 2008-06-03 20:22:19 +02:00
jse.c * Patch by Stephen Williams, 01 Apr 2004: 2004-04-15 23:14:49 +00:00
jse_priv.h * Patch by Stephen Williams, 01 Apr 2004: 2004-04-15 23:14:49 +00:00
Makefile Move "ar" flags to config.mk to allow for silent "make -s" 2006-10-09 01:02:05 +02:00
README.txt * Patch by Stephen Williams, 01 Apr 2004: 2004-04-15 23:14:49 +00:00
sdram.c Change initdram() return type to phys_size_t 2008-06-12 08:50:18 +02:00
u-boot.lds Big white-space cleanup. 2008-05-21 00:14:08 +02:00

JSE Configuration Details

Memory Bank 0 -- Flash chip
---------------------------

0xfff00000 - 0xffffffff

The flash chip is really only 512Kbytes, but the high address bit of
the 1Meg region is ignored, so the flash is replicated through the
region. Thus, this is consistent with a flash base address 0xfff80000.

The placement at the end is to be consistent with reset behavior,
where the processor itself initially uses this bus to load the branch
vector and start running.

On-Chip Memory
--------------

0xf4000000 - 0xf4000fff

The 405GPr includes a 4K on-chip memory that can be placed however
software chooses. I choose to place the memory at this address, to
keep it out of the cachable areas.


Memory Bank 1 -- SystemACE Controller
-------------------------------------

0xf0000000 - 0xf00fffff

The SystemACE chip is along on peripheral bank CS#1. We don't need
much space, but 1Meg is the smallest we can configure the chip to
allocate. We need it far away from the flash region, because this
region is set to be non-cached.


Internal Peripherals
--------------------

0xef600300 - 0xef6008ff

These are scattered various peripherals internal to the PPC405GPr
chip.

SDRAM
-----

0x00000000 - 0x07ffffff  (128 MBytes)