u-boot/board/jse
Stefan Roese a47a12becf Move arch/ppc to arch/powerpc
As discussed on the list, move "arch/ppc" to "arch/powerpc" to
better match the Linux directory structure.

Please note that this patch also changes the "ppc" target in
MAKEALL to "powerpc" to match this new infrastructure. But "ppc"
is kept as an alias for now, to not break compatibility with
scripts using this name.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Anatolij Gustschin <agust@denx.de>
2010-04-21 23:42:38 +02:00
..
config.mk * Patch by Stephen Williams, 01 Apr 2004: 2004-04-15 23:14:49 +00:00
flash.c rename CFG_ macros to CONFIG_SYS 2008-10-18 21:54:03 +02:00
host_bridge.c * Code cleanup, mostly for GCC-3.3.x 2004-12-31 09:32:47 +00:00
init.S ppc4xx: Big cleanup of PPC4xx defines 2009-09-11 10:35:58 +02:00
jse.c Move arch/ppc to arch/powerpc 2010-04-21 23:42:38 +02:00
jse_priv.h * Patch by Stephen Williams, 01 Apr 2004: 2004-04-15 23:14:49 +00:00
Makefile ppc4xx: Fix problems in some ppc4xx board Makefiles 2009-11-02 16:29:03 +01:00
README.txt * Patch by Stephen Williams, 01 Apr 2004: 2004-04-15 23:14:49 +00:00
sdram.c Move arch/ppc to arch/powerpc 2010-04-21 23:42:38 +02:00

JSE Configuration Details

Memory Bank 0 -- Flash chip
---------------------------

0xfff00000 - 0xffffffff

The flash chip is really only 512Kbytes, but the high address bit of
the 1Meg region is ignored, so the flash is replicated through the
region. Thus, this is consistent with a flash base address 0xfff80000.

The placement at the end is to be consistent with reset behavior,
where the processor itself initially uses this bus to load the branch
vector and start running.

On-Chip Memory
--------------

0xf4000000 - 0xf4000fff

The 405GPr includes a 4K on-chip memory that can be placed however
software chooses. I choose to place the memory at this address, to
keep it out of the cachable areas.


Memory Bank 1 -- SystemACE Controller
-------------------------------------

0xf0000000 - 0xf00fffff

The SystemACE chip is along on peripheral bank CS#1. We don't need
much space, but 1Meg is the smallest we can configure the chip to
allocate. We need it far away from the flash region, because this
region is set to be non-cached.


Internal Peripherals
--------------------

0xef600300 - 0xef6008ff

These are scattered various peripherals internal to the PPC405GPr
chip.

SDRAM
-----

0x00000000 - 0x07ffffff  (128 MBytes)