u-boot/board/freescale/t4rdb
Chunhe Lan e6c334a7a4 powerpc/t4rdb: Add alternate serdes protocols to align with A-007186
A-007186: SerDes PLL is calibrated at reset. It is possible
for jitter to increase and cause the PLL to unlock when the
temperature delta from the time the PLL is calibrated exceeds
+56C/-66C when using X VDD of 1.35 V (or +70C/-80C when using
XnVDD of 1.5 V). No issues are seen with LC VCO. The protocols
only using Ring VCOs are impacted.

Workaround:
For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring
VCO, this need to use alternate serdes protocols. Alternate
option has the same functionality as the original option; the
only difference being LC VCO rather than Ring VCO.

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-06-05 12:56:13 -07:00
..
ddr.c powerpc/85xx: Add T4240RDB board support 2014-05-13 08:24:32 -07:00
ddr.h powerpc/85xx: Add T4240RDB board support 2014-05-13 08:24:32 -07:00
eth.c powerpc/t4rdb: Add alternate serdes protocols to align with A-007186 2014-06-05 12:56:13 -07:00
law.c powerpc/85xx: Add T4240RDB board support 2014-05-13 08:24:32 -07:00
Makefile powerpc/85xx: Add T4240RDB board support 2014-05-13 08:24:32 -07:00
pci.c powerpc/85xx: Add T4240RDB board support 2014-05-13 08:24:32 -07:00
t4_pbi.cfg powerpc/85xx: Add T4240RDB board support 2014-05-13 08:24:32 -07:00
t4_rcw.cfg powerpc/t4rdb: Add alternate serdes protocols to align with A-007186 2014-06-05 12:56:13 -07:00
t4rdb.h powerpc/85xx: Add T4240RDB board support 2014-05-13 08:24:32 -07:00
t4240rdb.c powerpc/85xx: Add T4240RDB board support 2014-05-13 08:24:32 -07:00
tlb.c powerpc/85xx: Add T4240RDB board support 2014-05-13 08:24:32 -07:00