As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
468 lines
12 KiB
C
468 lines
12 KiB
C
/*
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* (C) Copyright 2000, 2001, 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with
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* changes based on the file arch/powerpc/mbxboot/m8260_tty.c from the
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* Linux/PPC sources (m8260_tty.c had no copyright info in it).
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*/
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/*
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* Minimal serial functions needed to use one of the SMC ports
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* as serial console interface.
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*/
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#include <common.h>
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#include <mpc8260.h>
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#include <asm/cpm_8260.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_CONS_ON_SMC)
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#if CONFIG_CONS_INDEX == 1 /* Console on SMC1 */
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#define SMC_INDEX 0
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#define PROFF_SMC_BASE PROFF_SMC1_BASE
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#define PROFF_SMC PROFF_SMC1
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#define CPM_CR_SMC_PAGE CPM_CR_SMC1_PAGE
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#define CPM_CR_SMC_SBLOCK CPM_CR_SMC1_SBLOCK
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#define CMXSMR_MASK (CMXSMR_SMC1|CMXSMR_SMC1CS_MSK)
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#define CMXSMR_VALUE CMXSMR_SMC1CS_BRG7
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#elif CONFIG_CONS_INDEX == 2 /* Console on SMC2 */
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#define SMC_INDEX 1
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#define PROFF_SMC_BASE PROFF_SMC2_BASE
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#define PROFF_SMC PROFF_SMC2
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#define CPM_CR_SMC_PAGE CPM_CR_SMC2_PAGE
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#define CPM_CR_SMC_SBLOCK CPM_CR_SMC2_SBLOCK
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#define CMXSMR_MASK (CMXSMR_SMC2|CMXSMR_SMC2CS_MSK)
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#define CMXSMR_VALUE CMXSMR_SMC2CS_BRG8
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#else
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#error "console not correctly defined"
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#endif
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#if !defined(CONFIG_SYS_SMC_RXBUFLEN)
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#define CONFIG_SYS_SMC_RXBUFLEN 1
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#define CONFIG_SYS_MAXIDLE 0
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#else
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#if !defined(CONFIG_SYS_MAXIDLE)
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#error "you must define CONFIG_SYS_MAXIDLE"
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#endif
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#endif
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typedef volatile struct serialbuffer {
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cbd_t rxbd; /* Rx BD */
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cbd_t txbd; /* Tx BD */
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uint rxindex; /* index for next character to read */
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volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
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volatile uchar txbuf; /* tx buffers */
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} serialbuffer_t;
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/* map rs_table index to baud rate generator index */
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static unsigned char brg_map[] = {
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6, /* BRG7 for SMC1 */
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7, /* BRG8 for SMC2 */
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0, /* BRG1 for SCC1 */
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1, /* BRG1 for SCC2 */
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2, /* BRG1 for SCC3 */
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3, /* BRG1 for SCC4 */
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};
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int serial_init (void)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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volatile smc_t *sp;
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volatile smc_uart_t *up;
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volatile cpm8260_t *cp = &(im->im_cpm);
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uint dpaddr;
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volatile serialbuffer_t *rtx;
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/* initialize pointers to SMC */
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sp = (smc_t *) &(im->im_smc[SMC_INDEX]);
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*(ushort *)(&im->im_dprambase[PROFF_SMC_BASE]) = PROFF_SMC;
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up = (smc_uart_t *)&im->im_dprambase[PROFF_SMC];
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/* Disable transmitter/receiver. */
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sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
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/* NOTE: I/O port pins are set up via the iop_conf_tab[] table */
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/* Allocate space for two buffer descriptors in the DP ram.
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* damm: allocating space after the two buffers for rx/tx data
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*/
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/* allocate size of struct serialbuffer with bd rx/tx,
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* buffer rx/tx and rx index
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*/
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dpaddr = m8260_cpm_dpalloc((sizeof(serialbuffer_t)), 16);
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rtx = (serialbuffer_t *)&im->im_dprambase[dpaddr];
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/* Set the physical address of the host memory buffers in
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* the buffer descriptors.
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*/
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rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf;
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rtx->rxbd.cbd_sc = 0;
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rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf;
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rtx->txbd.cbd_sc = 0;
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/* Set up the uart parameters in the parameter ram. */
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up->smc_rbase = dpaddr;
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up->smc_tbase = dpaddr+sizeof(cbd_t);
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up->smc_rfcr = CPMFCR_EB;
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up->smc_tfcr = CPMFCR_EB;
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up->smc_brklen = 0;
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up->smc_brkec = 0;
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up->smc_brkcr = 0;
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/* Set UART mode, 8 bit, no parity, one stop.
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* Enable receive and transmit.
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*/
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sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
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/* Mask all interrupts and remove anything pending. */
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sp->smc_smcm = 0;
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sp->smc_smce = 0xff;
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/* put the SMC channel into NMSI (non multiplexd serial interface)
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* mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17).
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*/
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im->im_cpmux.cmx_smr = (im->im_cpmux.cmx_smr&~CMXSMR_MASK)|CMXSMR_VALUE;
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/* Set up the baud rate generator. */
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serial_setbrg ();
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/* Make the first buffer the only buffer. */
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rtx->txbd.cbd_sc |= BD_SC_WRAP;
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rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
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/* single/multi character receive. */
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up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN;
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up->smc_maxidl = CONFIG_SYS_MAXIDLE;
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rtx->rxindex = 0;
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/* Initialize Tx/Rx parameters. */
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while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
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;
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cp->cp_cpcr = mk_cr_cmd(CPM_CR_SMC_PAGE, CPM_CR_SMC_SBLOCK,
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0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
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while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
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;
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/* Enable transmitter/receiver. */
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sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
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return (0);
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}
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void
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serial_setbrg (void)
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{
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#if defined(CONFIG_CONS_USE_EXTC)
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m8260_cpm_extcbrg(brg_map[SMC_INDEX], gd->baudrate,
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CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
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#else
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m8260_cpm_setbrg(brg_map[SMC_INDEX], gd->baudrate);
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#endif
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}
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void
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serial_putc(const char c)
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{
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volatile smc_uart_t *up;
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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volatile serialbuffer_t *rtx;
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if (c == '\n')
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serial_putc ('\r');
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up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
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rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase];
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/* Wait for last character to go. */
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while (rtx->txbd.cbd_sc & BD_SC_READY & BD_SC_READY)
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;
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rtx->txbuf = c;
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rtx->txbd.cbd_datlen = 1;
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rtx->txbd.cbd_sc |= BD_SC_READY;
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}
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void
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serial_puts (const char *s)
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{
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while (*s) {
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serial_putc (*s++);
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}
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}
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int
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serial_getc(void)
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{
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volatile smc_uart_t *up;
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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volatile serialbuffer_t *rtx;
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unsigned char c;
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up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
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rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase];
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/* Wait for character to show up. */
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while (rtx->rxbd.cbd_sc & BD_SC_EMPTY)
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;
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/* the characters are read one by one,
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* use the rxindex to know the next char to deliver
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*/
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c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr + rtx->rxindex);
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rtx->rxindex++;
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/* check if all char are readout, then make prepare for next receive */
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if (rtx->rxindex >= rtx->rxbd.cbd_datlen) {
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rtx->rxindex = 0;
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rtx->rxbd.cbd_sc |= BD_SC_EMPTY;
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}
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return(c);
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}
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int
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serial_tstc()
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{
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volatile smc_uart_t *up;
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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volatile serialbuffer_t *rtx;
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up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
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rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase];
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return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY);
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}
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#endif /* CONFIG_CONS_ON_SMC */
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#if defined(CONFIG_KGDB_ON_SMC)
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#if defined(CONFIG_CONS_ON_SMC) && CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX
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#error Whoops! serial console and kgdb are on the same smc serial port
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#endif
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#if CONFIG_KGDB_INDEX == 1 /* KGDB Port on SMC1 */
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#define KGDB_SMC_INDEX 0
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#define KGDB_PROFF_SMC_BASE PROFF_SMC1_BASE
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#define KGDB_PROFF_SMC PROFF_SMC1
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#define KGDB_CPM_CR_SMC_PAGE CPM_CR_SMC1_PAGE
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#define KGDB_CPM_CR_SMC_SBLOCK CPM_CR_SMC1_SBLOCK
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#define KGDB_CMXSMR_MASK (CMXSMR_SMC1|CMXSMR_SMC1CS_MSK)
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#define KGDB_CMXSMR_VALUE CMXSMR_SMC1CS_BRG7
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#elif CONFIG_KGDB_INDEX == 2 /* KGDB Port on SMC2 */
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#define KGDB_SMC_INDEX 1
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#define KGDB_PROFF_SMC_BASE PROFF_SMC2_BASE
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#define KGDB_PROFF_SMC PROFF_SMC2
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#define KGDB_CPM_CR_SMC_PAGE CPM_CR_SMC2_PAGE
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#define KGDB_CPM_CR_SMC_SBLOCK CPM_CR_SMC2_SBLOCK
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#define KGDB_CMXSMR_MASK (CMXSMR_SMC2|CMXSMR_SMC2CS_MSK)
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#define KGDB_CMXSMR_VALUE CMXSMR_SMC2CS_BRG8
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#else
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#error "console not correctly defined"
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#endif
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void
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kgdb_serial_init (void)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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volatile smc_t *sp;
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volatile smc_uart_t *up;
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volatile cbd_t *tbdf, *rbdf;
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volatile cpm8260_t *cp = &(im->im_cpm);
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uint dpaddr, speed = CONFIG_KGDB_BAUDRATE;
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char *s, *e;
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if ((s = getenv("kgdbrate")) != NULL && *s != '\0') {
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ulong rate = simple_strtoul(s, &e, 10);
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if (e > s && *e == '\0')
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speed = rate;
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}
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/* initialize pointers to SMC */
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sp = (smc_t *) &(im->im_smc[KGDB_SMC_INDEX]);
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*(ushort *)(&im->im_dprambase[KGDB_PROFF_SMC_BASE]) = KGDB_PROFF_SMC;
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up = (smc_uart_t *)&im->im_dprambase[KGDB_PROFF_SMC];
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/* Disable transmitter/receiver. */
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sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
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/* NOTE: I/O port pins are set up via the iop_conf_tab[] table */
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/* Allocate space for two buffer descriptors in the DP ram.
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* damm: allocating space after the two buffers for rx/tx data
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*/
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dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
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/* Set the physical address of the host memory buffers in
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* the buffer descriptors.
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*/
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rbdf = (cbd_t *)&im->im_dprambase[dpaddr];
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rbdf->cbd_bufaddr = (uint) (rbdf+2);
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rbdf->cbd_sc = 0;
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tbdf = rbdf + 1;
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tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
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tbdf->cbd_sc = 0;
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/* Set up the uart parameters in the parameter ram. */
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up->smc_rbase = dpaddr;
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up->smc_tbase = dpaddr+sizeof(cbd_t);
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up->smc_rfcr = CPMFCR_EB;
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up->smc_tfcr = CPMFCR_EB;
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up->smc_brklen = 0;
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up->smc_brkec = 0;
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up->smc_brkcr = 0;
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/* Set UART mode, 8 bit, no parity, one stop.
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* Enable receive and transmit.
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*/
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sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
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/* Mask all interrupts and remove anything pending. */
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sp->smc_smcm = 0;
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sp->smc_smce = 0xff;
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/* put the SMC channel into NMSI (non multiplexd serial interface)
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* mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17).
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*/
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im->im_cpmux.cmx_smr =
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(im->im_cpmux.cmx_smr & ~KGDB_CMXSMR_MASK) | KGDB_CMXSMR_VALUE;
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/* Set up the baud rate generator. */
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#if defined(CONFIG_KGDB_USE_EXTC)
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m8260_cpm_extcbrg(brg_map[KGDB_SMC_INDEX], speed,
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CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL);
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#else
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m8260_cpm_setbrg(brg_map[KGDB_SMC_INDEX], speed);
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#endif
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/* Make the first buffer the only buffer. */
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tbdf->cbd_sc |= BD_SC_WRAP;
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rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
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/* Single character receive. */
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up->smc_mrblr = 1;
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up->smc_maxidl = 0;
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/* Initialize Tx/Rx parameters. */
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while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
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;
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cp->cp_cpcr = mk_cr_cmd(KGDB_CPM_CR_SMC_PAGE, KGDB_CPM_CR_SMC_SBLOCK,
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0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
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while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
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;
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/* Enable transmitter/receiver. */
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sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
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printf("SMC%d at %dbps ", CONFIG_KGDB_INDEX, speed);
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}
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void
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putDebugChar(const char c)
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{
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volatile cbd_t *tbdf;
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volatile char *buf;
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volatile smc_uart_t *up;
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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if (c == '\n')
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putDebugChar ('\r');
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up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]);
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tbdf = (cbd_t *)&im->im_dprambase[up->smc_tbase];
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/* Wait for last character to go. */
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buf = (char *)tbdf->cbd_bufaddr;
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while (tbdf->cbd_sc & BD_SC_READY)
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;
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*buf = c;
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tbdf->cbd_datlen = 1;
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tbdf->cbd_sc |= BD_SC_READY;
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}
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void
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putDebugStr (const char *s)
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{
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while (*s) {
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putDebugChar (*s++);
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}
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}
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int
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getDebugChar(void)
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{
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volatile cbd_t *rbdf;
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volatile unsigned char *buf;
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volatile smc_uart_t *up;
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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unsigned char c;
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up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]);
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rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase];
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/* Wait for character to show up. */
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buf = (unsigned char *)rbdf->cbd_bufaddr;
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while (rbdf->cbd_sc & BD_SC_EMPTY)
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;
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c = *buf;
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rbdf->cbd_sc |= BD_SC_EMPTY;
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return(c);
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}
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|
void
|
|
kgdb_interruptible(int yes)
|
|
{
|
|
return;
|
|
}
|
|
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|
#endif /* CONFIG_KGDB_ON_SMC */
|