436 lines
10 KiB
ArmAsm
436 lines
10 KiB
ArmAsm
/*
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* Copyright 2008-2012 Freescale Semiconductor, Inc.
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* Kumar Gala <kumar.gala@freescale.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <mpc85xx.h>
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#include <version.h>
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#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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/* To boot secondary cpus, we need a place for them to start up.
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* Normally, they start at 0xfffffffc, but that's usually the
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* firmware, and we don't want to have to run the firmware again.
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* Instead, the primary cpu will set the BPTR to point here to
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* this page. We then set up the core, and head to
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* start_secondary. Note that this means that the code below
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* must never exceed 1023 instructions (the branch at the end
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* would then be the 1024th).
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*/
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.globl __secondary_start_page
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.align 12
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__secondary_start_page:
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/* First do some preliminary setup */
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lis r3, HID0_EMCP@h /* enable machine check */
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#ifndef CONFIG_E500MC
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ori r3,r3,HID0_TBEN@l /* enable Timebase */
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#endif
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#ifdef CONFIG_PHYS_64BIT
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ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
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#endif
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mtspr SPRN_HID0,r3
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#ifndef CONFIG_E500MC
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li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
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mfspr r0,PVR
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andi. r0,r0,0xff
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cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */
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blt 1f
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/* Set MBDD bit also */
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ori r3, r3, HID1_MBDD@l
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1:
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mtspr SPRN_HID1,r3
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
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mfspr r3,977
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oris r3,r3,0x0100
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mtspr 977,r3
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
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mfspr r3,SPRN_SVR
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rlwinm r3,r3,0,0xff
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li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
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cmpw r3,r4
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beq 1f
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#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
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li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
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cmpw r3,r4
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beq 1f
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#endif
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/* Not a supported revision affected by erratum */
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b 2f
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1: /* Erratum says set bits 55:60 to 001001 */
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msync
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isync
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mfspr r3,976
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li r4,0x48
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rlwimi r3,r4,0,0x1f8
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mtspr 976,r3
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isync
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2:
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#endif
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/* Enable branch prediction */
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lis r3,BUCSR_ENABLE@h
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ori r3,r3,BUCSR_ENABLE@l
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mtspr SPRN_BUCSR,r3
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/* Ensure TB is 0 */
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li r3,0
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mttbl r3
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mttbu r3
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/* Enable/invalidate the I-Cache */
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lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
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ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
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mtspr SPRN_L1CSR1,r2
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1:
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mfspr r3,SPRN_L1CSR1
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and. r1,r3,r2
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bne 1b
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lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
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ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
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mtspr SPRN_L1CSR1,r3
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isync
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2:
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mfspr r3,SPRN_L1CSR1
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andi. r1,r3,L1CSR1_ICE@l
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beq 2b
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/* Enable/invalidate the D-Cache */
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lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
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ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
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mtspr SPRN_L1CSR0,r2
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1:
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mfspr r3,SPRN_L1CSR0
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and. r1,r3,r2
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bne 1b
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lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
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ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
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mtspr SPRN_L1CSR0,r3
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isync
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2:
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mfspr r3,SPRN_L1CSR0
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andi. r1,r3,L1CSR0_DCE@l
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beq 2b
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#define toreset(x) (x - __secondary_start_page + 0xfffff000)
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/* get our PIR to figure out our table entry */
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lis r3,toreset(__spin_table)@h
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ori r3,r3,toreset(__spin_table)@l
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/* r10 has the base address for the entry */
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mfspr r0,SPRN_PIR
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#if defined(CONFIG_E6500)
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/*
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* PIR definition for E6500
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* 0-17 Reserved (logic 0s)
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* 8-19 CHIP_ID, 2’b00 - SoC 1
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* all others - reserved
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* 20-24 CLUSTER_ID 5’b00000 - CCM 1
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* all others - reserved
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* 25-26 CORE_CLUSTER_ID 2’b00 - cluster 1
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* 2’b01 - cluster 2
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* 2’b10 - cluster 3
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* 2’b11 - cluster 4
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* 27-28 CORE_ID 2’b00 - core 0
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* 2’b01 - core 1
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* 2’b10 - core 2
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* 2’b11 - core 3
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* 29-31 THREAD_ID 3’b000 - thread 0
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* 3’b001 - thread 1
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*/
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rlwinm r4,r0,29,25,31
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#elif defined(CONFIG_E500MC)
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rlwinm r4,r0,27,27,31
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#else
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mr r4,r0
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#endif
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slwi r8,r4,5
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add r10,r3,r8
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#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
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/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
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slwi r8,r4,1
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addi r8,r8,32
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mtspr L1CSR2,r8
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#endif
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#ifdef CONFIG_E6500
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mfspr r0,SPRN_PIR
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/*
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* core 0 thread 0: pir reset value 0x00, new pir 0
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* core 0 thread 1: pir reset value 0x01, new pir 1
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* core 1 thread 0: pir reset value 0x08, new pir 2
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* core 1 thread 1: pir reset value 0x09, new pir 3
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* core 2 thread 0: pir reset value 0x10, new pir 4
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* core 2 thread 1: pir reset value 0x11, new pir 5
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* etc.
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*
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* Only thread 0 of each core will be running, updating PIR doesn't
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* need to deal with the thread bits.
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*/
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rlwinm r4,r0,30,24,30
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#endif
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mtspr SPRN_PIR,r4 /* write to PIR register */
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#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
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defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
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/*
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* CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
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* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
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* also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
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*/
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mfspr r3,SPRN_SVR
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rlwinm r6,r3,24,~0x800 /* clear E bit */
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lis r5,SVR_P4080@h
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ori r5,r5,SVR_P4080@l
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cmpw r6,r5
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bne 1f
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rlwinm r3,r3,0,0xf0
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li r5,0x30
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cmpw r3,r5
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bge 2f
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1:
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#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
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lis r3,toreset(enable_cpu_a011_workaround)@ha
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lwz r3,toreset(enable_cpu_a011_workaround)@l(r3)
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cmpwi r3,0
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beq 2f
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#endif
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mfspr r3,L1CSR2
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oris r3,r3,(L1CSR2_DCWS)@h
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mtspr L1CSR2,r3
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2:
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#endif
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#ifdef CONFIG_BACKSIDE_L2_CACHE
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/* skip L2 setup on P2040/P2040E as they have no L2 */
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mfspr r3,SPRN_SVR
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rlwinm r6,r3,24,~0x800 /* clear E bit of SVR */
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lis r3,SVR_P2040@h
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ori r3,r3,SVR_P2040@l
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cmpw r6,r3
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beq 3f
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/* Enable/invalidate the L2 cache */
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msync
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lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
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ori r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
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mtspr SPRN_L2CSR0,r2
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1:
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mfspr r3,SPRN_L2CSR0
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and. r1,r3,r2
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bne 1b
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#ifdef CONFIG_SYS_CACHE_STASHING
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/* set stash id to (coreID) * 2 + 32 + L2 (1) */
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addi r3,r8,1
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mtspr SPRN_L2CSR1,r3
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#endif
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lis r3,CONFIG_SYS_INIT_L2CSR0@h
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ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l
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mtspr SPRN_L2CSR0,r3
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isync
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2:
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mfspr r3,SPRN_L2CSR0
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andis. r1,r3,L2CSR0_L2E@h
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beq 2b
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#endif
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3:
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#define EPAPR_MAGIC (0x45504150)
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#define ENTRY_ADDR_UPPER 0
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#define ENTRY_ADDR_LOWER 4
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#define ENTRY_R3_UPPER 8
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#define ENTRY_R3_LOWER 12
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#define ENTRY_RESV 16
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#define ENTRY_PIR 20
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#define ENTRY_R6_UPPER 24
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#define ENTRY_R6_LOWER 28
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#define ENTRY_SIZE 32
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/* setup the entry */
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li r3,0
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li r8,1
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stw r4,ENTRY_PIR(r10)
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stw r3,ENTRY_ADDR_UPPER(r10)
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stw r8,ENTRY_ADDR_LOWER(r10)
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stw r3,ENTRY_R3_UPPER(r10)
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stw r4,ENTRY_R3_LOWER(r10)
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stw r3,ENTRY_R6_UPPER(r10)
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stw r3,ENTRY_R6_LOWER(r10)
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/* load r13 with the address of the 'bootpg' in SDRAM */
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lis r13,toreset(__bootpg_addr)@h
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ori r13,r13,toreset(__bootpg_addr)@l
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lwz r13,0(r13)
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/* setup mapping for AS = 1, and jump there */
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lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
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mtspr SPRN_MAS0,r11
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lis r11,(MAS1_VALID|MAS1_IPROT)@h
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ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
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mtspr SPRN_MAS1,r11
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oris r11,r13,(MAS2_I|MAS2_G)@h
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ori r11,r13,(MAS2_I|MAS2_G)@l
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mtspr SPRN_MAS2,r11
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oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
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ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
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mtspr SPRN_MAS3,r11
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tlbwe
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bl 1f
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1: mflr r11
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/*
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* OR in 0xfff to create a mask of the bootpg SDRAM address. We use
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* this mask to fixup the cpu spin table and the address that we want
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* to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the
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* bootpg is at 0x7ffff000 in SDRAM.
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*/
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ori r13,r13,0xfff
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and r11, r11, r13
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and r10, r10, r13
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addi r11,r11,(2f-1b)
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mfmsr r13
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ori r12,r13,MSR_IS|MSR_DS@l
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mtspr SPRN_SRR0,r11
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mtspr SPRN_SRR1,r12
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rfi
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/* spin waiting for addr */
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2:
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lwz r4,ENTRY_ADDR_LOWER(r10)
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andi. r11,r4,1
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bne 2b
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isync
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/* setup IVORs to match fixed offsets */
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#include "fixed_ivor.S"
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/* get the upper bits of the addr */
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lwz r11,ENTRY_ADDR_UPPER(r10)
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/* setup branch addr */
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mtspr SPRN_SRR0,r4
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/* mark the entry as released */
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li r8,3
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stw r8,ENTRY_ADDR_LOWER(r10)
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/* mask by ~64M to setup our tlb we will jump to */
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rlwinm r12,r4,0,0,5
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/* setup r3, r4, r5, r6, r7, r8, r9 */
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lwz r3,ENTRY_R3_LOWER(r10)
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li r4,0
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li r5,0
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lwz r6,ENTRY_R6_LOWER(r10)
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lis r7,(64*1024*1024)@h
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li r8,0
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li r9,0
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/* load up the pir */
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lwz r0,ENTRY_PIR(r10)
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mtspr SPRN_PIR,r0
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mfspr r0,SPRN_PIR
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stw r0,ENTRY_PIR(r10)
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mtspr IVPR,r12
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/*
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* Coming here, we know the cpu has one TLB mapping in TLB1[0]
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* which maps 0xfffff000-0xffffffff one-to-one. We set up a
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* second mapping that maps addr 1:1 for 64M, and then we jump to
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* addr
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*/
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lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
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mtspr SPRN_MAS0,r10
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lis r10,(MAS1_VALID|MAS1_IPROT)@h
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ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
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mtspr SPRN_MAS1,r10
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/* WIMGE = 0b00000 for now */
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mtspr SPRN_MAS2,r12
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ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
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mtspr SPRN_MAS3,r12
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#ifdef CONFIG_ENABLE_36BIT_PHYS
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mtspr SPRN_MAS7,r11
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#endif
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tlbwe
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/* Now we have another mapping for this page, so we jump to that
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* mapping
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*/
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mtspr SPRN_SRR1,r13
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rfi
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/*
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* Allocate some space for the SDRAM address of the bootpg.
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* This variable has to be in the boot page so that it can
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* be accessed by secondary cores when they come out of reset.
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*/
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.globl __bootpg_addr
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__bootpg_addr:
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.long 0
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.align L1_CACHE_SHIFT
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.globl __spin_table
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__spin_table:
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.space CONFIG_MAX_CPUS*ENTRY_SIZE
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/*
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* This variable is set by cpu_init_r() after parsing hwconfig
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* to enable workaround for erratum NMG_CPU_A011.
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*/
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.align L1_CACHE_SHIFT
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.global enable_cpu_a011_workaround
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enable_cpu_a011_workaround:
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.long 1
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/* Fill in the empty space. The actual reset vector is
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* the last word of the page */
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__secondary_start_code_end:
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.space 4092 - (__secondary_start_code_end - __secondary_start_page)
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__secondary_reset_vector:
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b __secondary_start_page
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