Zhichun Hua 21a257b9b3 armv8: Fix TCR macros for shareability attribute ... For ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bit position [13:12] of TCR_ELx register. Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>		2015-07-20 11:44:40 -07:00
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asm	armv8: Fix TCR macros for shareability attribute	2015-07-20 11:44:40 -07:00
debug	arm: debug: replace license blocks with SPDX	2014-10-26 22:22:09 +01:00