Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
265 lines
5.9 KiB
C
265 lines
5.9 KiB
C
/*
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* (C) Copyright 2000-2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
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* Scott McNutt <smcnutt@psyent.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <nios2.h>
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#include <nios2-io.h>
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#include <asm/types.h>
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#include <asm/io.h>
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#include <asm/ptrace.h>
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#include <common.h>
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#include <command.h>
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#include <watchdog.h>
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#ifdef CONFIG_STATUS_LED
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#include <status_led.h>
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#endif
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#if defined(CONFIG_SYS_NIOS_TMRBASE) && !defined(CONFIG_SYS_NIOS_TMRIRQ)
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#error CONFIG_SYS_NIOS_TMRIRQ not defined (see documentation)
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#endif
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/****************************************************************************/
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struct irq_action {
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interrupt_handler_t *handler;
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void *arg;
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int count;
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};
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static struct irq_action vecs[32];
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/*************************************************************************/
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volatile ulong timestamp = 0;
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void reset_timer (void)
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{
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nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE;
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/* From Embedded Peripherals Handbook:
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*
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* "When the hardware is configured with Writeable period
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* disabled, writing to one of the period_n registers causes
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* the counter to reset to the fixed Timeout Period specified
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* at system generation time."
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*
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* Here we force a reload to prevent early timeouts from
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* get_timer() when the interrupt period is greater than
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* than 1 msec.
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*
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* Simply write to periodl with its own value to force an
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* internal counter reload, THEN reset the timestamp.
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*/
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writel (readl (&tmr->periodl), &tmr->periodl);
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timestamp = 0;
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/* From Embedded Peripherals Handbook:
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*
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* "Writing to one of the period_n registers stops the internal
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* counter, except when the hardware is configured with Start/Stop
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* control bits off. If Start/Stop control bits is off, writing
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* either register does not stop the counter."
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*
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* In order to accomodate either configuration, the control
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* register is re-written. If the counter is stopped, it will
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* be restarted. If it is running, the write is essentially
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* a nop.
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*/
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writel (NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START,
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&tmr->control);
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}
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ulong get_timer (ulong base)
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{
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WATCHDOG_RESET ();
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return (timestamp - base);
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}
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/*
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* This function is derived from Blackfin code (read timebase as long long).
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* On Nios2 it just returns the timer value.
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*/
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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/*
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* This function is derived from Blackfin code.
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* On Nios2 it returns the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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ulong tbclk;
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tbclk = CONFIG_SYS_HZ;
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return tbclk;
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}
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/* The board must handle this interrupt if a timer is not
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* provided.
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*/
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#if defined(CONFIG_SYS_NIOS_TMRBASE)
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void tmr_isr (void *arg)
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{
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nios_timer_t *tmr = (nios_timer_t *)arg;
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/* Interrupt is cleared by writing anything to the
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* status register.
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*/
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writel (0, &tmr->status);
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timestamp += CONFIG_SYS_NIOS_TMRMS;
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#ifdef CONFIG_STATUS_LED
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status_led_tick(timestamp);
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#endif
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}
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static void tmr_init (void)
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{
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nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE;
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writel (0, &tmr->status);
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writel (0, &tmr->control);
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writel (NIOS_TIMER_STOP, &tmr->control);
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#if defined(CONFIG_SYS_NIOS_TMRCNT)
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writel (CONFIG_SYS_NIOS_TMRCNT & 0xffff, &tmr->periodl);
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writel ((CONFIG_SYS_NIOS_TMRCNT >> 16) & 0xffff, &tmr->periodh);
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#endif
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writel (NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START,
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&tmr->control);
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irq_install_handler (CONFIG_SYS_NIOS_TMRIRQ, tmr_isr, (void *)tmr);
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}
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#endif /* CONFIG_SYS_NIOS_TMRBASE */
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/*************************************************************************/
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int disable_interrupts (void)
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{
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int val = rdctl (CTL_STATUS);
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wrctl (CTL_STATUS, val & ~STATUS_IE);
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return (val & STATUS_IE);
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}
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void enable_interrupts( void )
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{
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int val = rdctl (CTL_STATUS);
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wrctl (CTL_STATUS, val | STATUS_IE);
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}
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void external_interrupt (struct pt_regs *regs)
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{
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unsigned irqs;
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struct irq_action *act;
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/* Evaluate only irqs that are both enabled AND pending */
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irqs = rdctl (CTL_IENABLE) & rdctl (CTL_IPENDING);
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act = vecs;
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/* Assume (as does the Nios2 HAL) that bit 0 is highest
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* priority. NOTE: There is ALWAYS a handler assigned
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* (the default if no other).
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*/
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while (irqs) {
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if (irqs & 1) {
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act->handler (act->arg);
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act->count++;
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}
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irqs >>=1;
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act++;
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}
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}
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static void def_hdlr (void *arg)
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{
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unsigned irqs = rdctl (CTL_IENABLE);
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/* Disable the individual interrupt -- with gratuitous
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* warning.
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*/
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irqs &= ~(1 << (int)arg);
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wrctl (CTL_IENABLE, irqs);
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printf ("WARNING: Disabling unhandled interrupt: %d\n",
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(int)arg);
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}
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/*************************************************************************/
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void irq_install_handler (int irq, interrupt_handler_t *hdlr, void *arg)
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{
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int flag;
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struct irq_action *act;
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unsigned ena = rdctl (CTL_IENABLE);
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if ((irq < 0) || (irq > 31))
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return;
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act = &vecs[irq];
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flag = disable_interrupts ();
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if (hdlr) {
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act->handler = hdlr;
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act->arg = arg;
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ena |= (1 << irq); /* enable */
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} else {
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act->handler = def_hdlr;
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act->arg = (void *)irq;
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ena &= ~(1 << irq); /* disable */
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}
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wrctl (CTL_IENABLE, ena);
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if (flag) enable_interrupts ();
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}
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int interrupt_init (void)
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{
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int i;
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/* Assign the default handler to all */
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for (i = 0; i < 32; i++) {
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vecs[i].handler = def_hdlr;
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vecs[i].arg = (void *)i;
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vecs[i].count = 0;
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}
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#if defined(CONFIG_SYS_NIOS_TMRBASE)
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tmr_init ();
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#endif
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enable_interrupts ();
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return (0);
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}
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/*************************************************************************/
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#if defined(CONFIG_CMD_IRQ)
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int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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int i;
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struct irq_action *act = vecs;
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printf ("\nInterrupt-Information:\n\n");
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printf ("Nr Routine Arg Count\n");
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printf ("-----------------------------\n");
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for (i=0; i<32; i++) {
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if (act->handler != def_hdlr) {
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printf ("%02d %08lx %08lx %d\n",
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i,
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(ulong)act->handler,
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(ulong)act->arg,
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act->count);
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}
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act++;
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}
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printf ("\n");
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return (0);
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}
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#endif
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