u-boot/arch/arm/mach-keystone
Karicheri, Muralidharan bcdc1c8376 keystone: k2h/e/l: Fix DMA coherency for QM PDSP
commit 1f807a9f32 ("ARM: keystone2: Refactor MSMC macros to avoid
left under a macro KS2_MSMC_SEGMENT_QM_PDSP which is no longer valid.
This, in effect disabled DMA coherency for QM PDSP.

Given that msmc_k2hkle_common_setup is valid for all K2H/K/L/E SoCs,
the #ifdef should been removed in the first place. Do the same.

Fixes: 1f807a9f32 ("ARM: keystone2: Refactor MSMC macros to avoid #ifdeffery")
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-07-25 12:00:05 -04:00
..
include/mach ARM: k2g: Configure reset mux to device reset 2016-06-02 21:42:19 -04:00
clock.c ARM: keystone2: K2G: Add support for different arm/device speeds 2016-03-14 19:18:44 -04:00
cmd_clock.c ARM: keystone2: Use common definition for clk_get_rate 2015-08-12 20:47:55 -04:00
cmd_ddr3.c ARM: keystone: move SoC sources to mach-keystone 2015-02-21 08:23:52 -05:00
cmd_mon.c ARM: keystone2: Split monitor code / command code 2016-03-16 15:03:15 -04:00
cmd_poweroff.c ARM: keystone2: Switch to using the poweroff command 2016-03-16 15:03:32 -04:00
config.mk ARM: keystone2: Use dtb images by default 2015-10-22 14:22:11 -04:00
ddr3.c ARM: k2g: Add ddr3 info 2015-10-22 14:22:18 -04:00
ddr3_spd.c ARM: keystone2: use detected ddr3a size 2016-03-14 19:18:45 -04:00
init.c keystone: k2h/e/l: Fix DMA coherency for QM PDSP 2016-07-25 12:00:05 -04:00
Kconfig ARM: k2g: Add kconfig support 2015-10-22 14:22:13 -04:00
keystone.c ARM: keystone2: Switch to using the poweroff command 2016-03-16 15:03:32 -04:00
Makefile ARM: keystone2: Only link cmd_ddr3.o on non-SPL builds 2016-03-16 15:03:34 -04:00
mon.c ARM: keystone2: Split monitor code / command code 2016-03-16 15:03:15 -04:00
msmc.c ARM: keystone: move SoC sources to mach-keystone 2015-02-21 08:23:52 -05:00
psc.c ARM: keystone2: psc: introduce function to hold and release module in reset. 2016-03-14 19:18:36 -04:00