165 lines
3.5 KiB
ArmAsm
165 lines
3.5 KiB
ArmAsm
/*
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* Copyright (C) 2005-2006 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm/sysreg.h>
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#ifndef PART_SPECIFIC_BOOTSTRAP
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# define PART_SPECIFIC_BOOTSTRAP
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#endif
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#define SYSREG_MMUCR_I_OFFSET 2
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#define SYSREG_MMUCR_S_OFFSET 4
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#define SR_INIT (SYSREG_BIT(GM) | SYSREG_BIT(EM) | SYSREG_BIT(M0))
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#define CPUCR_INIT (SYSREG_BIT(BI) | SYSREG_BIT(BE) \
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| SYSREG_BIT(FE) | SYSREG_BIT(RE) \
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| SYSREG_BIT(IBE) | SYSREG_BIT(IEE))
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.text
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.global _start
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_start:
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PART_SPECIFIC_BOOTSTRAP
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/* Reset the Status Register */
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mov r0, lo(SR_INIT)
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orh r0, hi(SR_INIT)
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mtsr SYSREG_SR, r0
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/* Reset CPUCR and invalidate the BTB */
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mov r2, CPUCR_INIT
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mtsr SYSREG_CPUCR, r2
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/* Flush the caches */
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mov r1, 0
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cache r1[4], 8
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cache r1[0], 0
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sync 0
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/* Reset the MMU to default settings */
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mov r0, SYSREG_BIT(MMUCR_S) | SYSREG_BIT(MMUCR_I)
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mtsr SYSREG_MMUCR, r0
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/* Internal RAM should not need any initialization. We might
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have to initialize external RAM here if the part doesn't
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have internal RAM (or we may use the data cache) */
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/* Jump to cacheable segment */
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lddpc pc, 1f
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.align 2
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1: .long 2f
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2: lddpc sp, sp_init
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/* Initialize the GOT pointer */
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lddpc r6, got_init
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3: rsub r6, pc
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/* Let's go */
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rjmp board_init_f
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.align 2
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.type sp_init,@object
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sp_init:
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.long CFG_INIT_SP_ADDR
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got_init:
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.long 3b - _GLOBAL_OFFSET_TABLE_
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/*
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* void relocate_code(new_sp, new_gd, monitor_addr)
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*
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* Relocate the u-boot image into RAM and continue from there.
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* Does not return.
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*/
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.global relocate_code
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.type relocate_code,@function
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relocate_code:
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mov sp, r12 /* use new stack */
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mov r12, r11 /* save new_gd */
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mov r11, r10 /* save destination address */
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/* copy .text section and flush the cache along the way */
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lda.w r8, _text
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lda.w r9, _etext
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sub lr, r10, r8 /* relocation offset */
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1: ldm r8++, r0-r3
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stm r10, r0-r3
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sub r10, -16
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ldm r8++, r0-r3
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stm r10, r0-r3
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sub r10, -16
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cp.w r8, r9
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cache r10[-4], 0x0d /* dcache clean/invalidate */
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cache r10[-4], 0x01 /* icache invalidate */
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brlt 1b
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/* flush write buffer */
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sync 0
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/* copy data sections */
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lda.w r9, _edata
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1: ld.d r0, r8++
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st.d r10++, r0
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cp.w r8, r9
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brlt 1b
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/* zero out .bss */
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mov r0, 0
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mov r1, 0
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lda.w r9, _end
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sub r9, r8
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1: st.d r10++, r0
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sub r9, 8
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brgt 1b
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/* jump to RAM */
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sub r0, pc, . - in_ram
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add pc, r0, lr
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.align 2
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in_ram:
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/* find the new GOT and relocate it */
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lddpc r6, got_init_reloc
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3: rsub r6, pc
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mov r8, r6
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lda.w r9, _egot
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lda.w r10, _got
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sub r9, r10
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1: ld.w r0, r8[0]
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add r0, lr
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st.w r8++, r0
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sub r9, 4
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brgt 1b
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/* Move the exception handlers */
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mfsr r2, SYSREG_EVBA
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add r2, lr
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mtsr SYSREG_EVBA, r2
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/* Do the rest of the initialization sequence */
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call board_init_r
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.align 2
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got_init_reloc:
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.long 3b - _GLOBAL_OFFSET_TABLE_
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