Add code necessary to program the FPGA part of SoCFPGA from U-Boot with an RBF blob. This patch also integrates the code into the FPGA driver framework in U-Boot so it can be used via the 'fpga' command. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> V2: Move the not-CPU specific stuff into drivers/fpga/ and base this on the cleaned up altera FPGA support.
149 lines
3.2 KiB
C
149 lines
3.2 KiB
C
/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <altera.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/system_manager.h>
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#include <asm/arch/dwmmc.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct socfpga_system_manager *sysmgr_regs =
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
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return 0;
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}
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/*
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* DesignWare Ethernet initialization
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*/
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#ifdef CONFIG_DESIGNWARE_ETH
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int cpu_eth_init(bd_t *bis)
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{
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#if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
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const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
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#elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
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const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
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#else
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#error "Incorrect CONFIG_EMAC_BASE value!"
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#endif
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/* Initialize EMAC. This needs to be done at least once per boot. */
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/*
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* Putting the EMAC controller to reset when configuring the PHY
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* interface select at System Manager
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*/
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socfpga_emac_reset(1);
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/* Clearing emac0 PHY interface select to 0 */
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clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
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SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
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/* configure to PHY interface select choosed */
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setbits_le32(&sysmgr_regs->emacgrp_ctrl,
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SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
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/* Release the EMAC controller from reset */
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socfpga_emac_reset(0);
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/* initialize and register the emac */
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return designware_initialize(CONFIG_EMAC_BASE,
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CONFIG_PHY_INTERFACE_MODE);
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}
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#endif
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#ifdef CONFIG_DWMMC
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/*
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* Initializes MMC controllers.
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* to override, implement board_mmc_init()
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*/
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int cpu_mmc_init(bd_t *bis)
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{
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return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
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CONFIG_HPS_SDMMC_BUSWIDTH, 0);
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}
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#endif
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#if defined(CONFIG_DISPLAY_CPUINFO)
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/*
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* Print CPU information
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*/
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int print_cpuinfo(void)
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{
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puts("CPU: Altera SoCFPGA Platform\n");
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return 0;
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}
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#endif
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#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
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defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
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int overwrite_console(void)
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{
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return 0;
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}
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#endif
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#ifdef CONFIG_FPGA
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/*
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* FPGA programming support for SoC FPGA Cyclone V
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*/
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static Altera_desc altera_fpga[] = {
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{
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/* Family */
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Altera_SoCFPGA,
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/* Interface type */
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fast_passive_parallel,
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/* No limitation as additional data will be ignored */
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-1,
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/* No device function table */
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NULL,
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/* Base interface address specified in driver */
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NULL,
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/* No cookie implementation */
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0
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},
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};
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/* add device descriptor to FPGA device table */
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static void socfpga_fpga_add(void)
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{
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int i;
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fpga_init();
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for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
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fpga_add(fpga_altera, &altera_fpga[i]);
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}
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#else
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static inline void socfpga_fpga_add(void) {}
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#endif
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int arch_cpu_init(void)
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{
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/*
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* If the HW watchdog is NOT enabled, make sure it is not running,
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* for example because it was enabled in the preloader. This might
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* trigger a watchdog-triggered reboot of Linux kernel later.
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*/
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#ifndef CONFIG_HW_WATCHDOG
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socfpga_watchdog_reset();
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#endif
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return 0;
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}
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int misc_init_r(void)
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{
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/* Add device descriptor to FPGA device table */
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socfpga_fpga_add();
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return 0;
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}
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