This patch merges the ECC handling (ECC parity byte writing) into one file (ecc.c) for all PPC4xx SDRAM controllers except for PPC440EPx/GRx. This exception is because only those PPC's use the completely different Denali SDRAM controller core. Previously we had two routines to generate/write the ECC parity bytes. With this patch we now only have one core function left. Tested on Kilauea (no ECC) and Katmai (with and without ECC). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Felix Radensky <felix@embedded-sol.com> Cc: Grant Erickson <gerickson@nuovations.com> Cc: Pieter Voorthuijsen <pv@prodrive.nl>
186 lines
5.1 KiB
C
186 lines
5.1 KiB
C
/*
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* Copyright (c) 2008 Nuovation System Designs, LLC
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* Grant Erickson <gerickson@nuovations.com>
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*
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* (C) Copyright 2005-2009
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2002
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* Jun Gu, Artesyn Technology, jung@artesyncp.com
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*
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* (C) Copyright 2001
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* Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will abe useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Description:
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* This file implements generic DRAM ECC initialization for
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* PowerPC processors using a SDRAM DDR/DDR2 controller,
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* including the 405EX(r), 440GP/GX/EP/GR, 440SP(E), and
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* 460EX/GT.
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*/
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#include <common.h>
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#include <ppc4xx.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include "ecc.h"
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#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) || \
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defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
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#if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC)
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#if defined(CONFIG_405EX)
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/*
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* Currently only 405EX uses 16bit data bus width as an alternative
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* option to 32bit data width (SDRAM0_MCOPT1_WDTH)
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*/
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#define SDRAM_DATA_ALT_WIDTH 2
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#else
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#define SDRAM_DATA_ALT_WIDTH 8
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#endif
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static void wait_ddr_idle(void)
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{
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u32 val;
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do {
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mfsdram(SDRAM_MCSTAT, val);
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} while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
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}
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static void program_ecc_addr(unsigned long start_address,
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unsigned long num_bytes,
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unsigned long tlb_word2_i_value)
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{
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unsigned long current_address;
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unsigned long end_address;
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unsigned long address_increment;
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unsigned long mcopt1;
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char str[] = "ECC generation -";
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char slash[] = "\\|/-\\|/-";
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int loop = 0;
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int loopi = 0;
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current_address = start_address;
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mfsdram(SDRAM_MCOPT1, mcopt1);
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if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
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mtsdram(SDRAM_MCOPT1,
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(mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
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sync();
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eieio();
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wait_ddr_idle();
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puts(str);
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#ifdef CONFIG_440
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if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
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#endif
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/* ECC bit set method for non-cached memory */
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if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
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address_increment = 4;
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else
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address_increment = SDRAM_DATA_ALT_WIDTH;
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end_address = current_address + num_bytes;
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while (current_address < end_address) {
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*((unsigned long *)current_address) = 0;
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current_address += address_increment;
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if ((loop++ % (2 << 20)) == 0) {
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putc('\b');
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putc(slash[loopi++ % 8]);
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}
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}
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#ifdef CONFIG_440
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} else {
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/* ECC bit set method for cached memory */
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dcbz_area(start_address, num_bytes);
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/* Write modified dcache lines back to memory */
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clean_dcache_range(start_address, start_address + num_bytes);
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}
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#endif /* CONFIG_440 */
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blank_string(strlen(str));
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sync();
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eieio();
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wait_ddr_idle();
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/* clear ECC error repoting registers */
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mtsdram(SDRAM_ECCES, 0xffffffff);
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mtdcr(0x4c, 0xffffffff);
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mtsdram(SDRAM_MCOPT1,
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(mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
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sync();
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eieio();
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wait_ddr_idle();
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}
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}
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#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
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void ecc_init(unsigned long * const start, unsigned long size)
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{
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/*
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* Init ECC with cache disabled (on PPC's with IBM DDR
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* controller (non DDR2), not tested with cache enabled yet
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*/
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program_ecc_addr((u32)start, size, TLB_WORD2_I_ENABLE);
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}
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#endif
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#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
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void do_program_ecc(unsigned long tlb_word2_i_value)
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{
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unsigned long mcopt1;
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unsigned long mcopt2;
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unsigned long mcstat;
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phys_size_t memsize = sdram_memsize();
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if (memsize > CONFIG_MAX_MEM_MAPPED) {
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printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n");
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return;
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}
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mfsdram(SDRAM_MCOPT1, mcopt1);
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mfsdram(SDRAM_MCOPT2, mcopt2);
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if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
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/* DDR controller must be enabled and not in self-refresh. */
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mfsdram(SDRAM_MCSTAT, mcstat);
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if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
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&& ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
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&& ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
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== (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
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program_ecc_addr(0, memsize, tlb_word2_i_value);
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}
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}
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}
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#endif
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#endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */
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#endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)... */
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