This patch consolidates the 405 and 440 parts of the NAND booting code selected via CONFIG_NAND_SPL. Now common code is used to initialize the SDRAM by calling initdram() and to "copy/relocate" to SDRAM/OCM/etc. Only *after* running from this location, nand_boot() is called. Please note that the initsdram() call is now moved from nand_boot.c to start.S. I experienced problems with some boards like Kilauea (405EX), which don't have internal SRAM (OCM) and relocation needs to be done to SDRAM before the NAND controller can get accessed. When initdram() is called later on in nand_boot(), this can lead to problems with variables in the bss sections like nand_ecc_pos[]. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Scott Wood <scottwood@freescale.com>
256 lines
6.6 KiB
C
256 lines
6.6 KiB
C
/*
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* (C) Copyright 2006-2008
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <nand.h>
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#define CFG_NAND_READ_DELAY \
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{ volatile int dummy; int i; for (i=0; i<10000; i++) dummy = i; }
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static int nand_ecc_pos[] = CFG_NAND_ECCPOS;
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extern void board_nand_init(struct nand_chip *nand);
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#if (CFG_NAND_PAGE_SIZE <= 512)
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/*
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* NAND command for small page NAND devices (512)
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*/
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static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
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{
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struct nand_chip *this = mtd->priv;
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int page_addr = page + block * CFG_NAND_PAGE_COUNT;
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if (this->dev_ready)
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this->dev_ready(mtd);
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else
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CFG_NAND_READ_DELAY;
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/* Begin command latch cycle */
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this->hwcontrol(mtd, NAND_CTL_SETCLE);
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this->write_byte(mtd, cmd);
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/* Set ALE and clear CLE to start address cycle */
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this->hwcontrol(mtd, NAND_CTL_CLRCLE);
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this->hwcontrol(mtd, NAND_CTL_SETALE);
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/* Column address */
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this->write_byte(mtd, offs); /* A[7:0] */
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this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[16:9] */
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this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[24:17] */
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#ifdef CFG_NAND_4_ADDR_CYCLE
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/* One more address cycle for devices > 32MiB */
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this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f)); /* A[xx:25] */
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#endif
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/* Latch in address */
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this->hwcontrol(mtd, NAND_CTL_CLRALE);
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/*
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* Wait a while for the data to be ready
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*/
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if (this->dev_ready)
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this->dev_ready(mtd);
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else
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CFG_NAND_READ_DELAY;
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return 0;
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}
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#else
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/*
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* NAND command for large page NAND devices (2k)
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*/
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static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
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{
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struct nand_chip *this = mtd->priv;
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int page_offs = offs;
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int page_addr = page + block * CFG_NAND_PAGE_COUNT;
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if (this->dev_ready)
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this->dev_ready(mtd);
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else
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CFG_NAND_READ_DELAY;
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/* Emulate NAND_CMD_READOOB */
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if (cmd == NAND_CMD_READOOB) {
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page_offs += CFG_NAND_PAGE_SIZE;
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cmd = NAND_CMD_READ0;
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}
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/* Begin command latch cycle */
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this->hwcontrol(mtd, NAND_CTL_SETCLE);
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this->write_byte(mtd, cmd);
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/* Set ALE and clear CLE to start address cycle */
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this->hwcontrol(mtd, NAND_CTL_CLRCLE);
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this->hwcontrol(mtd, NAND_CTL_SETALE);
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/* Column address */
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this->write_byte(mtd, page_offs & 0xff); /* A[7:0] */
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this->write_byte(mtd, (uchar)((page_offs >> 8) & 0xff)); /* A[11:9] */
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/* Row address */
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this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[19:12] */
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this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[27:20] */
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#ifdef CFG_NAND_5_ADDR_CYCLE
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/* One more address cycle for devices > 128MiB */
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this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f)); /* A[xx:28] */
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#endif
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/* Latch in address */
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this->hwcontrol(mtd, NAND_CTL_CLRALE);
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/* Begin command latch cycle */
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this->hwcontrol(mtd, NAND_CTL_SETCLE);
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/* Write out the start read command */
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this->write_byte(mtd, NAND_CMD_READSTART);
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/* End command latch cycle */
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this->hwcontrol(mtd, NAND_CTL_CLRCLE);
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/*
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* Wait a while for the data to be ready
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*/
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if (this->dev_ready)
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this->dev_ready(mtd);
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else
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CFG_NAND_READ_DELAY;
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return 0;
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}
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#endif
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static int nand_is_bad_block(struct mtd_info *mtd, int block)
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{
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struct nand_chip *this = mtd->priv;
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nand_command(mtd, block, 0, CFG_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
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/*
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* Read one byte
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*/
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if (this->read_byte(mtd) != 0xff)
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return 1;
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return 0;
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}
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static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
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{
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struct nand_chip *this = mtd->priv;
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u_char *ecc_calc;
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u_char *ecc_code;
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u_char *oob_data;
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int i;
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int eccsize = CFG_NAND_ECCSIZE;
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int eccbytes = CFG_NAND_ECCBYTES;
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int eccsteps = CFG_NAND_ECCSTEPS;
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uint8_t *p = dst;
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int stat;
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nand_command(mtd, block, page, 0, NAND_CMD_READ0);
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/* No malloc available for now, just use some temporary locations
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* in SDRAM
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*/
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ecc_calc = (u_char *)(CFG_SDRAM_BASE + 0x10000);
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ecc_code = ecc_calc + 0x100;
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oob_data = ecc_calc + 0x200;
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for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
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this->enable_hwecc(mtd, NAND_ECC_READ);
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this->read_buf(mtd, p, eccsize);
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this->calculate_ecc(mtd, p, &ecc_calc[i]);
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}
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this->read_buf(mtd, oob_data, CFG_NAND_OOBSIZE);
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/* Pick the ECC bytes out of the oob data */
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for (i = 0; i < CFG_NAND_ECCTOTAL; i++)
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ecc_code[i] = oob_data[nand_ecc_pos[i]];
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eccsteps = CFG_NAND_ECCSTEPS;
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p = dst;
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for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
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/* No chance to do something with the possible error message
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* from correct_data(). We just hope that all possible errors
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* are corrected by this routine.
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*/
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stat = this->correct_data(mtd, p, &ecc_code[i], &ecc_calc[i]);
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}
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return 0;
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}
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static int nand_load(struct mtd_info *mtd, int offs, int uboot_size, uchar *dst)
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{
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int block;
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int blockcopy_count;
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int page;
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/*
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* offs has to be aligned to a block address!
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*/
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block = offs / CFG_NAND_BLOCK_SIZE;
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blockcopy_count = 0;
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while (blockcopy_count < (uboot_size / CFG_NAND_BLOCK_SIZE)) {
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if (!nand_is_bad_block(mtd, block)) {
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/*
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* Skip bad blocks
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*/
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for (page = 0; page < CFG_NAND_PAGE_COUNT; page++) {
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nand_read_page(mtd, block, page, dst);
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dst += CFG_NAND_PAGE_SIZE;
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}
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blockcopy_count++;
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}
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block++;
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}
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return 0;
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}
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/*
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* The main entry for NAND booting. It's necessary that SDRAM is already
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* configured and available since this code loads the main U-Boot image
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* from NAND into SDRAM and starts it from there.
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*/
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void nand_boot(void)
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{
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struct nand_chip nand_chip;
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nand_info_t nand_info;
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int ret;
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void (*uboot)(void);
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/*
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* Init board specific nand support
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*/
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nand_info.priv = &nand_chip;
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nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CFG_NAND_BASE;
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nand_chip.dev_ready = NULL; /* preset to NULL */
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board_nand_init(&nand_chip);
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/*
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* Load U-Boot image from NAND into RAM
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*/
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ret = nand_load(&nand_info, CFG_NAND_U_BOOT_OFFS, CFG_NAND_U_BOOT_SIZE,
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(uchar *)CFG_NAND_U_BOOT_DST);
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/*
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* Jump to U-Boot image
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*/
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uboot = (void (*)(void))CFG_NAND_U_BOOT_START;
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(*uboot)();
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}
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