Stephen George f110fe940c powerpc/85xx: Adding configuration for DCSRCR to enable 32M access ... Configuring DCSRCR to define the DCSR space to be 1G instead of the default 4M. DCSRCR only allows selection of either 4M or 1G. Most DCSR registers are within 4M but the Nexus trace buffer is located at offset 16M within the DCSR. Configuring the LAW to be 32M to allow access to the Nexus trace buffer. No TLB modification is required since accessing the Nexus trace buffer from within u-boot is not required. Signed-off-by: Stephen George <stephen.george@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>		2011-07-29 08:53:37 -05:00
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corenet_ds.c	powerpc/85xx: Fix compile errors if CONFIG_SYS_DPAA_QBMAN isn't set	2011-07-11 13:24:19 -05:00
ddr.c	powerpc/mpc85xx: Display a warning for unsupported DDR data rates	2011-07-11 13:24:20 -05:00
law.c	powerpc/85xx: Adding configuration for DCSRCR to enable 32M access	2011-07-29 08:53:37 -05:00
Makefile	powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code)	2011-04-27 22:29:04 -05:00
p3041ds_ddr.c	powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code)	2011-04-27 22:29:04 -05:00
p4080ds_ddr.c	powerpc/85xx: Update fixed DDR3 timing table for P4080DS	2011-04-04 09:24:41 -05:00
p5020ds_ddr.c	powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code)	2011-04-27 22:29:04 -05:00
pci.c	powerpc/85xx: Rework corenet_ds pci_init_board to use common FSL PCIe code	2011-01-14 01:32:21 -06:00
tlb.c	powerpc/85xx: Fix compile errors if CONFIG_SYS_{B,Q}MAN_MEM_PHYS aren't set	2011-07-11 13:24:19 -05:00