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Paul Burton 7953354b07 MIPS: Join the coherent domain when a CM is present 
MIPS Linux expects the bootloader to leave the boot CPU a member of the
coherent domain when running on a system with a CM, and we will need to
do so if we wish to make use of IOCUs to have cache-coherent DMA in
U-Boot (and on some systems there is no choice in that matter). When a
CM is present, join the coherent domain after completing cache
initialisation.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
 		2016-09-21 15:04:04 +02:00
..
cpu MIPS: Map CM Global Control Registers 2016-09-21 15:04:04 +02:00
dts mips: xilfpga: Add device tree files 2016-09-21 14:55:14 +02:00
include/asm MIPS: Join the coherent domain when a CM is present 2016-09-21 15:04:04 +02:00
lib MIPS: Join the coherent domain when a CM is present 2016-09-21 15:04:04 +02:00
mach-ath79 MIPS: ath79: Use mach_cpu_init instead of arch_cpu_init 2016-09-21 15:04:04 +02:00
mach-au1x00 net: mii: Use spatch to update miiphy_register 2016-08-15 15:26:33 -05:00
mach-pic32 clk: convert API to match reset/mailbox style 2016-06-19 17:05:55 -06:00
Kconfig MIPS: L2 cache support 2016-09-21 15:04:04 +02:00
Makefile MIPS: add tune for MIPS 34kc 2016-05-31 09:38:11 +02:00
config.mk MIPS: provide a default u-boot-spl.lds 2016-05-31 09:38:11 +02:00