u-boot/arch/arm/cpu/armv8
Prabhakar Kushwaha b401736463 armv8: ls2085a: Add workaround of errata A009635
If the core runs at higher than x3 speed of the platform, there is
possiblity about sev instruction to getting missed by other cores.
This is because of SoC Run Control block may not able to sample
the EVENTI(Sev) signals.

Configure Run Control and EPU to periodically send out EVENTI signals to
wake up A57 cores.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:12 -08:00
..
fsl-layerscape armv8: ls2085a: Add workaround of errata A009635 2015-11-30 09:11:12 -08:00
hisilicon hisilicon: hi6220: Add a hi6220 pinmux driver. 2015-08-12 20:48:00 -04:00
zynqmp zynqmp: mp: Add support for booting R5 from any address 2015-11-19 10:42:45 +01:00
cache.S arm: armv8 correct value passed to __asm_dcache_all 2015-09-12 09:03:39 +02:00
cache_v8.c armv8/layerscape: Update MMU table with execute-never bits 2015-11-30 09:11:11 -08:00
config.mk ARM: move -march=* and -mtune= options to arch/arm/Makefile 2015-03-27 16:55:22 +01:00
cpu.c arm64: core support 2014-01-09 16:08:44 +01:00
exceptions.S remove unnecessary version.h includes 2015-03-24 10:50:50 -04:00
generic_timer.c armv8/fsl-lsch3: Implement workaround for erratum A008585 2015-04-23 08:55:54 -07:00
Kconfig armv8/vexpress64: make multientry conditional 2015-03-09 11:13:29 -04:00
Makefile armv8/fsl_lsch3: Change arch to fsl-layerscape 2015-10-29 10:34:00 -07:00
start.S armv8: Make COUNTER_FREQUENCY optional 2015-09-16 16:10:22 -07:00
tlb.S remove unnecessary version.h includes 2015-03-24 10:50:50 -04:00
transition.S remove unnecessary version.h includes 2015-03-24 10:50:50 -04:00
u-boot-spl.lds armv8/ls2085aqds: NAND boot support 2015-04-23 16:46:50 -07:00
u-boot.lds arm64: core support 2014-01-09 16:08:44 +01:00