f56348af5d
The purpose of this patch is to prepare for adding the OMAP4 architecture, which is Cortex A9 Cortex A8 and A9 both belong to the armv7 architecture, hence the name change. The two architectures are similar enough that substantial code can be shared. Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Steve Sakoman <steve@sakoman.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
51 lines
1.5 KiB
C
51 lines
1.5 KiB
C
/*
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* needed for arch/arm/cpu/armv7/mx51/lowlevel_init.S
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*
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* These should be auto-generated
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*/
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/* CCM */
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#define CLKCTL_CCR 0x00
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#define CLKCTL_CCDR 0x04
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#define CLKCTL_CSR 0x08
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#define CLKCTL_CCSR 0x0C
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#define CLKCTL_CACRR 0x10
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#define CLKCTL_CBCDR 0x14
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#define CLKCTL_CBCMR 0x18
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#define CLKCTL_CSCMR1 0x1C
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#define CLKCTL_CSCMR2 0x20
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#define CLKCTL_CSCDR1 0x24
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#define CLKCTL_CS1CDR 0x28
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#define CLKCTL_CS2CDR 0x2C
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#define CLKCTL_CDCDR 0x30
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#define CLKCTL_CHSCCDR 0x34
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#define CLKCTL_CSCDR2 0x38
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#define CLKCTL_CSCDR3 0x3C
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#define CLKCTL_CSCDR4 0x40
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#define CLKCTL_CWDR 0x44
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#define CLKCTL_CDHIPR 0x48
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#define CLKCTL_CDCR 0x4C
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#define CLKCTL_CTOR 0x50
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#define CLKCTL_CLPCR 0x54
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#define CLKCTL_CISR 0x58
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#define CLKCTL_CIMR 0x5C
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#define CLKCTL_CCOSR 0x60
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#define CLKCTL_CGPR 0x64
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#define CLKCTL_CCGR0 0x68
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#define CLKCTL_CCGR1 0x6C
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#define CLKCTL_CCGR2 0x70
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#define CLKCTL_CCGR3 0x74
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#define CLKCTL_CCGR4 0x78
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#define CLKCTL_CCGR5 0x7C
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#define CLKCTL_CCGR6 0x80
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#define CLKCTL_CMEOR 0x84
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/* DPLL */
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#define PLL_DP_CTL 0x00
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#define PLL_DP_CONFIG 0x04
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#define PLL_DP_OP 0x08
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#define PLL_DP_MFD 0x0C
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#define PLL_DP_MFN 0x10
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#define PLL_DP_HFS_OP 0x1C
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#define PLL_DP_HFS_MFD 0x20
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#define PLL_DP_HFS_MFN 0x24
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