Add a clock driver for Exynos7420 SoC. There are about 25 clock controller blocks in Exynos7420 out of which support for topc, top0 and peric1 blocks are added in this initial version of the driver. Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
15 lines
435 B
Makefile
15 lines
435 B
Makefile
#
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# Copyright (c) 2015 Google, Inc
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-$(CONFIG_CLK) += clk-uclass.o clk_fixed_rate.o
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obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
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obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
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obj-$(CONFIG_SANDBOX) += clk_sandbox.o
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obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
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obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
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obj-$(CONFIG_CLK_EXYNOS) += exynos/
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